一個適用於MPEG即時視訊系統之位元率控制演算法與架構設計

Abstract

位元率控制(rate control)對於影像視訊壓縮而言是個相當重要的研究主題，它在視訊品質的決定上扮演著關鍵性的角色，特別是在低位率的應用環境中。位元率控制的主要挑戰在於如何能在有限位元率的限制下壓縮視訊，並獲得最佳的視訊品質。儘管已經有相當多位元率控制的演算法被提出，但這些現存的方法幾乎都只著重在演算法層級上而沒有考量到積體電路實現與系統層級(system-level)的問題，同時也僅適合以軟體方式來實現，許多演算法的高運算複雜度，對於系統而言實現成本將會極高，而能否滿足即時(real-time)編碼的速度要求亦是一大疑問。有鑑於此，在本篇論文中我們針對MPEG-2視訊壓縮標準提出了一個新的位元率控制演算法與硬體架構，此演算法以一個簡單的位元率線性方程式為核心，利用巨集區塊(macroblock)與整張影像之複雜度(activity)間的比例關係，做為位元分配(bit allocation)的基礎。此演算法相較於MPEG-2標準TM5所定義的以及一些現存的其他方法而言，不僅運算複雜度降低、輸出影像資料流(bitstream)的位元變動率減小，同時影像品質與穩定度也都有提升。由於適合於積體電路實現，我們進一步提出了硬體設計及IP化的位元率控制模組MPEG-2系統解決方案。

Rate control is an important topic for video and image compression. It plays a key role in determining the video quality especially for the low bit-rate applications. The main challenge of rate control is to obtain the best video quality under the limited bit-rate constraint. Although a variety of rate control algorithms have been proposed, these present literatures almost only focused on the algorithm level and very few ones have considered the VLSI implementation and system-level issues. They were only suitable to be realized using software approach. Many rate control algorithms may not be easy to be implemented even to meet the real-time specification due to their high computational complexity. In this thesis, a new rate control algorithm and architecture is proposed, which using the relation of macroblock and picture activity for bit allocation that is derived from a simple bit-rate model. This algorithm features low computational complexity and the picture quality are improved while the fluctuations of generated video bit-counts are reduced compared to that of MPEG-2 TM5. Due to the suitability for VLSI implementation, the hardware architecture and the IP-based solution targeted for MPEG-2 are further proposed. 1.1 Overview of the development of image and video compression techniques 1 1.2 The rate control's role 3 1.3 Motivation 4 1.4 Outline of this thesis 5 Chapter 2 Rate Control Module in MPEG-2 Video Codec System and Algorithm Description 7 2.1 Introduction to digital video compression 7 2.2 Overview of MPEG-2 codec system 10 2.2.1 Compression algorithm principles 11 2.1.2 MPEG-2 codec system 12 2.1.3 Profiles and levels 13 2.3 Quantization and inverse quantization unit 14 2.3.1 Quantization unit 14 2.3.2 Inverse quantization unit 16 2.4 Description of rate control algorithm 17 2.4.1 Bit allocation and rate-distortion theory 18 2.4.2 Test Model 5 20 2.4.3 Related works and discussion 23 Chapter 3 The New Activity-Based Rate Control Algorithm 28 3.1 Algorithm description 29 3.1.1 Rate model and macroblock-level bit allocation 30 3.1.2 Adaptively update model parameter 33 3.1.3 Frame-level bit allocation 34 3.1.4 Complete algorithm 37 3.2 Simulation Results and comparison 40 3.2 Complexity reduction 46 Chapter 4 The VLSI Architecture and Implementation 51 4.1 Hardware implementation issue 51 4.2 System requirement 53 4.3 Algorithm modification for hardware implementation 56 4.4 Using logrithmic operation to implement multiplication and division 57 4.4.1 The conversion of logrithm operands 58 4.4.2 Transforming our algorithm into logrithm space 60 4.5 Architecture design 62 4.5.1 Activity-Measure unit 63 4.5.2 Frame-bit-Estimation unit 64 4.5.3 Quantizer-Generator unit 64 4.5.4 Update-Parameter unit 66 4.5.5 Data-Ram unit 67 4.6 I/O and timing diagram 68 4.7 Synthesis result 68 4.8 Comparison of processor-based and dedicated hardware solutions for rate control 71 Chapter 5 Consideration of IP design and Rate Control IP 73 5.1 Methodology for IP creation 74 5.2 Consideration of IP design for JPEG and MPEG-2 video codec systems 75 5.3 Rate Control IP 76 5.3.1 Configuration information and parameters 77 5.4 DCT-Rate Control Processor IP 78 Chapter 6 Conclusion and Future Work 81 6.1 Conclusion 81 6.2 Future work 82 References 83