完整後設資料紀錄
DC 欄位語言
dc.contributor.author陳哲生en_US
dc.contributor.authorChen Che-Shengen_US
dc.contributor.author溫瓖岸en_US
dc.contributor.authorKuei-Ann Chenen_US
dc.date.accessioned2014-12-12T02:23:12Z-
dc.date.available2014-12-12T02:23:12Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880428056en_US
dc.identifier.urihttp://hdl.handle.net/11536/65694-
dc.description.abstract在這篇論文中, 我們將討論到寛中頻帶接收器架構在2.4 GHz跳頻系統上之應用。 在本文中會提出一個系統模擬層次的設計流程。 我設計並比較三種不同的電壓控制振盪器依循相同的設計流程。在0.25 um CMOS的製程下,採用正補式交錯振盪器架構所得到的模擬結果如下,可調頻率範圍從2.25 GHz到2.37 GHz,輸出功率 –6 dBm,功率消耗 12.5 mW,相位雜訊在頻率位移1MHz是 –105 dBc/Hz。 最後將討論到類比電路跟數位系統的共同模擬。zh_TW
dc.description.abstractIn this thesis, the architecture of Wide-band IF receiver for 2.4 GHz FHSS system has been proposed. A design flow for system level simulation has been introduced. Three kinds of VCO have been designed and compared following a proposed design flow for oscillator design. Under 0.25 um CMOS technology, the simulated specifications of complementary cross-coupled oscillator include, tuning range from 2.25 GHz to 2.37 GHz, output power –6 dBm, power dissipation 12.5 mW, phase noise at 1MHz offset –105 dBc/Hz. Finally, a co-simulation of analog circuits and digital system has been proposed. Abstract 誌謝 Contents List of Figures List of Tables Chapter 1 Introduction 1-1 1.1 General Wireless Communication System 1-1 1.2 Fully Integration CMOS transceiver 1-2 1.3 Wireless System Design Flow 1-4 1.4 Thesis Overview 1-6 Chapter 2 RF Receiver Design 2-1 2.1 Receiver Specifications 2-1 2.2 Receiver Architectures 2-3 2.2.1 Heterodyne receiver 2-3 2.2.2 Homodyne receiver 2-7 2.2.3 Image-Reject receiver 2-8 2.3 A 2.4 GHz FHSS Receiver Design 2-11 2.3.1 Bluetooth radio specification 2-11 2.3.2 FHSS receiver design flow 2-12 Chapter 3 Voltage controlled Oscillator Design 3-1 3.1 Oscillator fundamentals 3-1 3.1.1 Models 3-1 3.1.2 Phase noise 3-3 3.1.3 Quality factor 3-5 3.2 Design considerations 3-5 3.2.1 Phase Noise LTI Model 3-5 3.2.2 Trade-offs 3-7 3.3 CMOS VCO Design for 2.4GHz 3-8 3.3.1 Design Methodology using ADS 3-8 3.3.2 Comparison of some VCO Structures 3-14 Chapter 4 A CMOS FHSS Receiver 4-1 4.1 The Determined Receiver 4-1 4.2 Voltage Controlled Oscillator 4-2 4.3 Low Noise Amplifier 4-4 4.4 Double-Balance Mixer 4-7 Chapter 5 System Performance Evaluation 5-1 5.1 Co-simulation in ADS 5-1 5.2 Modulation and Demodulation 5-1 5.3 Co-simulation with analog circuit 5-2 Chapter 6 Conclusions 6-1 6.1 Conclusions 6-1 6.2 Future works 6-1 Referencesen_US
dc.language.isoen_USen_US
dc.subject跳頻zh_TW
dc.subjectCMOSzh_TW
dc.subject接收器zh_TW
dc.subject藍芽zh_TW
dc.subject電壓控制振盪器zh_TW
dc.subject振盪器zh_TW
dc.subjectFHSSen_US
dc.subjectCMOSen_US
dc.subjectreceiveren_US
dc.subjectbluetoothen_US
dc.subjectVCOen_US
dc.subjectoscillatoren_US
dc.title2.4 GHz CMOS 跳頻接收器設計zh_TW
dc.titleA Design of 2.4 GHz CMOS FHSS Receiveren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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