完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 王忠勝 | en_US |
dc.contributor.author | Chung-Sheng Wang | en_US |
dc.contributor.author | 黃宇中 | en_US |
dc.contributor.author | Yu-Chung Huang | en_US |
dc.date.accessioned | 2014-12-12T02:23:12Z | - |
dc.date.available | 2014-12-12T02:23:12Z | - |
dc.date.issued | 1999 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT880428057 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/65695 | - |
dc.description.abstract | 本論文利用原有低電壓標準互補式金氧半電晶體(CMOS)製程實踐智慧電壓延伸型(Smart Voltage Extension, SVX)高電壓元件。在TSMC 0.6μm的標準CMOS技術下透過特殊的佈局方法,可得到耐壓為原製程正常工作電壓十倍左右的電晶體特性。為了瞭解此耐壓30V以上的高壓電晶體在不同元件佈局幾何參數下的導通及耐壓特性,採取兩種方式來研究:一是利用半導體技術電腦輔助設計(Technology Computer-Aided Design, TCAD)來模擬元件製程及其電性;一是利用量測電壓與電流來觀察對電性的影響。最後利用半導體工具軟體(AURORA)建立簡易SPICE模型並提出高壓電晶體在電路應用上可行性之探討。 | zh_TW |
dc.description.abstract | The thesis uses the SVX (Smart Voltage Extension) approach to implement the high-voltage devices without modifying the processing steps of a standard, low-voltage n-well CMOS (Complementary Metal Oxide Semiconductor) technology. Through the special layout techniques, high-voltage n-type MOS transistor is usually capable to sustain about 10 times the nominal voltage of the 0.6-micrometer standard CMOS technique provided by TSMC. In order to investigate the forward and breakdown characteristics of n type high-voltage transistors sustained voltage above 30volts with various ranges of layout parameters, two approaches are adopted. First, TCAD (Technology Computer-Aided Design) is utilized to simulate devices' processes and electrical characteristics. The other is the measurement about static characteristics of the high-voltage devices. At last, third level and BSIM SPICE models were also derived for the high-voltage transistors by the device's parameter exactor (AURORA). Beside, it will be mentioned that high-voltage transistor are dedicated to applications of circuit level, such as level shifters and ESD(Electrostatic Discharge) circuits. 英文摘要II 誌謝III 目錄IV 表目錄V 圖目錄VI 第 1 章 緒論1 第 2 章 元件結構與操作9 2.1 元件崩潰原理9 2.1.1 通道熱載子效應與崩潰機制10 2.1.2 累增型崩潰與游離積分值13 2.1.3 接面終端的影響14 2.2 REDUCED SURFACE FIELD原理17 2.3 橫向結構高壓金氧半電晶體在關閉狀態的操作原理19 2.3.1 第一操作區(VD<VP1)20 2.3.2 第二操作區(VP2>VD3VP1)20 2.3.3 第三操作區(VD3VP2)21 2.4 場板(FIELD PLATE)的應用21 2.5 元件之電阻模型23 2.5.1 金氧半電晶體通道電阻23 2.5.2 漂移區電阻24 2.5.3 汲極源極電阻24 第 3 章 設計、模擬分析與量測31 3.1 智慧電壓延伸型(SVX)高壓電晶體的設計31 3.1.1 初步崩潰電壓的估算31 3.1.2 佈局幾何參數的設計32 3.1.3 設計流程34 3.2 SVX高壓電晶體之模擬34 3.2.1 製程模擬35 3.2.2 電性模擬36 3.2.3 熱與衝撞游離模擬39 3.3 SVX高壓電晶體之模型40 3.3.1 n型高壓電晶體巨觀模型架構41 3.3.2 操作原理41 3.3.3 n型高壓電晶體簡易SPICE模型42 3.4 SVX元件電性量測43 3.4.1 電性量測系統架設43 3.4.2 電性量測結果討論45 第 4 章 結果討論與電路應用79 4.1 幾何結構對元件特性的影響79 4.2 量測電流(I)-電壓(V)曲線與SPICE模型的匹配80 4.3 SVX高壓電晶體在電路上的應用80 4.3.1 在致動器驅動電路上的應用81 4.3.2 在ESD(靜電放電防護)電路上的應用82 第 5 章 結論與未來方向90 附錄92 參考文獻98 | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 電壓延伸型 | zh_TW |
dc.subject | 高壓電晶體 | zh_TW |
dc.subject | SVX | en_US |
dc.subject | high-voltage transistor | en_US |
dc.title | CMOS高壓電晶體之研究 | zh_TW |
dc.title | A Study of High Voltage MOSFET in CMOS Technology | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |