新型被動式對數感測器之互補式金氧半影像讀出積體電路設計

Abstract

近年來，互補式金氧半影像感測器已經受到廣泛的關注，顧客對於微型化、低功率、低成本的需求成為其受到持續關注的主要原因。互補式金氧半影像感測器提供了整合超大型積體電路中各個系統在同一個晶片上潛在的機會，並且減少了電路版上積體電路元件的數量，降低包裝成本。一個包含時序控制器、感測器陣列、訊號處理器、類比至數位轉換器、數位介面的單晶片照相機已是可預期得，在標準邏輯電路電壓提供下，此單晶片照相機的功率消耗僅有數十毫瓦。 互補式金氧半影像感測器運用在高解析度方面，將會面臨圖素點尺寸過大的問題，因此，一個圖素點中只含兩個電晶體的架構被採用來克服此困難。由於僅減少圖素點中的電晶體數，所以可以保有原來的填滿係數（21%），同時減少圖素點的尺寸（6.15x6.05□m2）。有效區在P型離子佈植之外P-diffusion/N-well 的感光二極體被用來去除強光激發生成之過多載子對於鄰近圖素點的影響，並且減小由於鳥嘴所生成的漏電流。為了降低固定樣本雜訊和放大訊號，所以相關取樣電路技術和輸出放大器被採用。 以點五微米DPDM N-well製成，包含感測陣列、解碼器、讀出電路的128x128互補式金氧半影像感測器已經完成量測，圖素點讀出速度為10MHz，在5V的電壓供應下，功率消耗為64mW。

Recently, there has been a growing interest in CMOS image sensors. The major reason for this interest is the customer demand for miniaturized, low-power, and low-cost digital cameras. CMOS image sensors offer a great potential to integrate a significant amount of VLSI electronics on a single chip and reduce discrete components and packaging costs. It is now straightforward to envision a single-chip camera that has integrated timing and control electronics, sensor array, signal processing electronics, analog-to-digital converter (ADC) and full digital interface. Such a camera-on-a-chip will operate with standard logic supply voltages and consume power measured in the tens of milliwatts. The pixel size is the key point for CMOS image sensors in high-resolution applications. In this thesis, the structure of two-transistors in a pixel is proposed. Due to the reduction of the number of transistors in a pixel , the pixel size is as small as 6.15x6.05 □m2 and the fill factor is 21%. The P-diffusion/N-well with the P-implant region inside the thin-oxide region is proposed for the photodiode. It is anti-blooming and has low leakage current induced nearly the bird’s beak. The correlated double sampling (CDS) technique and output amplifier are used to reduce the fixed pattern noise (FPN) and amplify the signal voltage, respectively. A 128x128 CMOS image sensor including image array, decoder, readout circuit, fabricated by 0.5□m Double-Poly-Double-Metal (DPDM) N-well CMOS technology has been measured. The pixel rate is 10MHz, and power consumption is 64mW at 5V power supply. ABSTRACT (ENGLISH)………………………………………………iii CONTENTS………………………………………………………………….v TABLE CAPTIONS………………………………………………………vii FIGURE CAPTIONS…………………………………………………….vii CHAPTER 1 INTRODUCTION 1.1 BACKGROUND…………………………………………………………...1 1.2 MOTIVATION……………………………………………………………...3 1.3 ORGANIZATION OF THIS THESIS……………………………………...4 CHAPTER 2 REVIEW ON ACTVE PIXEL SENSOR AND READOUT METHODOLGY FOR CMOS TECHNOLOGY 2.1 GLOSSARY OF TERMS…………………………………………………6 2.2 ARCHITECUTRE………………………………………………………...8 2.3 IMAGE SENSOR DESIGN………………………………………………9 2.3.1 CMOS COMPATIBLE PN-JUNCTION PHOTODIODES……….9 2.3.2 PIXEL STRUCTURE AND CIRCUIT…………………………..11 2.3.3 COLUMN READOUT AMPLIFIER…………………………….12 2.3.4 BUFFERING IN THE OUTPUT SIGNAL PATH………………..13 2.3.5 DIGITAL DECODING LOGIC…………...……………………...13 2.4 TEST SETUP……………………………………………………………..13 CHAPTER 3 2-TRANSISTOR-PIXEL STRUCTURE AND CORRELATED READOUT AMPLIFIER FOR CMOS IMAGE SENSOR 3.1 ARCHITECTURE…………………………………………………………15 3.2 IMAGE SENSOR DESIGN………………………………………………..15 3.2.1 PIXEL STRUCTURE AND CIRCUIT……………………………..16 3.2.2 PIXEL OPERATION………………………………………………..17 3.2.3 COLUMN READOUT AMPLIFIER……………………………….18 3.2.4 OUTPUT AMPLIFIER……………………………………………...19 3.3 DIGITAL PART FOR PIXELS ACCESS…………………………………..22 3.4 SIMULATION RESULTS…………………………………………………..23 CHAPTER 4 EXPERIMENTAL RESULTS 4.1 LAYOUT DESCRIPTION…………………………………………………24 4.2 IMAGE DISPLAY SYSTEM SETUP……………………………………...25 4.3 EXPERIMENTAL RESULTS………………………………………………26 CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 5.1 CONCLUSIONS……………………………………………………………27 5.2 FUTURE WORKS………………………………………………………….27