鎳金屬矽化物催化結晶方法對低溫複晶矽薄膜電晶體

Abstract

利用鎳金屬矽化物催化結晶來製作高效能低溫複晶矽薄膜電晶體的方法已廣泛地被討論。目前所有有關的論文均只是在討論鎳金屬矽化物催化結晶的現象對於複晶矽薄膜電晶體特性之影響，但從實驗中我們發現元件尺寸、主動層的厚度甚至鎳金屬圖樣的大小以及鎳金屬距離通道(Channel)的遠近與元件的位置均會影響到複晶矽薄膜電晶體的特性。在本論文中，我們將就這些因素深入地討論，並且對於實驗結果，提出合理的模型來加以解釋。 在第一部份的物性分析中，我們首先就鎳金屬矽化物催化結晶後的矽薄膜做個介紹。從顯微鏡觀察得知，鎳金屬矽化物催化側向結晶的速率約為每小時1.3微米；從二次離子質譜儀（SIMS）中，我們測得鎳金屬在側向結晶後所殘留在複晶矽薄膜的含量約為1018/cm3；此外，從縱剖面穿透式電子顯微鏡影以及顯微鏡影像得之，不同厚度的非晶矽薄膜厚度將影響晶粒成長的方向。最後，我們將提出模型加以解釋這些現象以及鎳金屬矽化物催化側向結晶的機制。 在第二部分的電性討論中，我們從電性上證實了不同的元件尺寸、主動層的厚度、不同大小及遠近的鎳金屬圖樣以及元件的位置均會影響到薄膜電晶體的特性；同時，我們會提出模型詳加解釋。最後，運用氨氣(NH3)電漿鈍化處理之後，薄膜電晶體的電特性將可以有效地改善。由本論文的結果，我們可明確地證明，鎳金屬矽化物催化結晶方法可以製作高效能低溫複晶矽薄膜電晶體，但是諸如元件尺寸、主動層的厚度、不同大小及遠近的鎳金屬圖樣以及元件的位置需加以詳細仔細設計。

Low-temperature polycrystalline silicon thin film transistors fabricated by nickel silicide mediated crystallization (NMC) method have been widely studied. But, all related papers just discuss the effects of NMC method on the performance of poly-Si TFTs. However, we find that the dimension of device, the active layer thickness, the dimension of nickel pattern, the distance between channel and nickel pattern and the location of device would also affect the performance of poly-Si TFTs. In this thesis, these effects will be discussed thoroughly and models will be proposed to explain them. In the first section, we will introduce the phenomenon of Si film crystallized by NMC method. From OM images, we have inspected that the NMLC velocity is about 1.3um/hr. Then, from SIMS analysis, we have found that Ni concentration in NMLC region is about 1018 1/cm3. Besides, we have investigated the phenomenon of different thicknesses of a-Si films crystallized by NMLC method. From the cross sectional TEM and OM images, we have found that the orientations of grains would be seriously affected by thickness of a-Si thin film. Finally, we will propose a model to explain these phenomena and nickel silicide mediated lateral crystallization mechanisms. In the second section, we will prove that the dimension of device, the active layer thickness, the dimension of nickel pattern, the distance between channel and nickel pattern and the location of device will also affect the performance of poly-Si TFTs from electrical analyses. Meanwhile, models will also be proposed to explain them. Last, we will use NH3 plasma treatment to improve the performance of NMLC poly-Si TFTs. According to the results in this thesis, we can definitely indicate that NMLC is a good method to fabricate high performance low temperature poly-Si TFTs. However, the dimension of device, the active layer thickness, the dimension of nickel pattern, the distance between channel and nickel pattern and the location of device should be carefully designed. Introduction 1.1 Overview of Polycrystalline Silicon Thin-Film Transistors 1.2 Solid-Phase Crystallization of Amorphous Silicon 1.3 Crystallization by Excimer Laser Annealing 1.4 Metal Mediated Crystallization 1.5 Low Temperature Gate Oxide 1.6 Plasma Passivation of Poly-Si TFTs 1.7 Thesis Outline 1.8 Reference Chapter 2 Material Characteristics of Nickel Silicide Mediated Laterally Crystallized Amorphous Silicon 2.1 Introduction 2.2 Experimental Details 2.2.1 Samples for measuring crystallization velocity and optical microscope analyses 2.2.2 Samples for SIMS analyses 2.2.3 Samples for cross-sectional TEM analyses 2.3 Results and Discussions 2.3.1 Structure of nickel disilicide 2.3.2 Nickel disilicide mediated lateral crystallization mechanisms 2.3.3 Nickel disilicide mediated lateral crystallization velocity 2.3.4 SIMS analyses 2.3.5 Analyses of optical microscope (OM) images 2.3.6 Analyses of cross-sectional TEM images 2.3.7 Model for active layer thickness effect 2.4 Summary 2.5 Reference Chapter 3 Characteristics of Poly-Si TFTs Fabricated by NMLC method 3.1 Introduction 3.2 Experimental Details 3.2.1 Fabrication process of poly-Si TFTs made by NMLC with blanket Ni deposition 3.2.2 Fabrication process of poly-Si TFTs made by NMLC with double-sided Ni deposition and single-sided Ni deposition 3.3 Results and Discussions 3.3.1 Electrical properties of poly-Si TFTs fabricated by NMLC with blanket Ni deposition 3.3.1.1 Channel width effect on poly-Si TFTs fabricated by NMLC with blanket Ni deposition 3.3.1.2 Channel length effect on poly-Si TFTs fabricated by NMLC with blanket Ni deposition 3.3.1.3 NH3 plasma treatment effects on poly-Si TFTs fabricated by NMLC with blanket Ni deposition 3.3.2 Active layer thickness effect on poly-Si TFTs fabricated by NMLC with blanket Ni deposition 3.3.2.1 Electrical properties of poly-Si TFTs with different active layer thicknesses 3.3.2.2 Active layer thickness effect on poly-Si TFTs with NH3 plasma treatment 3.3.3 Nickel pattern width effect on NMLC velocity 3.3.4 Electrical properties of poly-Si TFTs fabricated by NMLC with double-sided Ni deposition 3.3.4.1 Pattern width effect on poly-Si TFTs fabricated by NMLC with double-sided Ni deposition 3.3.4.2 Channel length effect on poly-Si TFTs fabricated by NMLC with double-sided Ni deposition 3.3.4.3 NH3 plasma treatment effects on poly-Si TFTs fabricated by NMLC with double-sided Ni deposition 3.3.5 Electrical properties of poly-Si TFTs fabricated by NMLC with single-sided Ni deposition 3.3.5.1 Pattern width effect on poly-Si TFTs fabricated by NMLC with single-sided Ni deposition 3.3.5.2 Channel length effect on poly-Si TFTs fabricated by NMLC with single-sided Ni deposition 3.3.5.3 Electrical properties of poly-Si TFTs fabricated by NMLC with single-sided Ni deposition as source/drain reversed 3.3.5.4 NH3 plasma treatment effects on poly-Si TFTs fabricated by NMLC with single-sided Ni deposition 3.3.6 Comparison of the performance of poly-Si TFTs fabricated by NMLC with double-sided Ni deposition and single-sided Ni deposition 3.3.6.1 Electrical properties between poly-Si TFTs fabricated by NMLC with double-sided Ni deposition and single-sided Ni deposition 3.3.6.2 NH3 plasma treatment effects on poly-Si TFTs fabricated by NMLC with double-sided Ni deposition and single-sided Ni deposition 3.4 Summary 3.5 Reference Chapter 4 Summary and Conclusions Appendix FiguresTables