超薄閘極氧化層之製程相關可靠度研究

Abstract

本論文研究的方向，主要著重於探討超薄閘極氧化層元件的閘極氧化層可靠度之研究。一般說來, 閘極介電層厚度之所以隨著每個新的CMOS技術世代而持續縮減的原因主要是為了解決短通道效應(short channel effects)及獲得較高的電流驅動能力(driving capability)，隨著閘極氧化層厚度不斷的變薄，對於閘極氧化層可靠度的需求也就越來越高，所以超薄氧化層的可靠性問題也就成為當今積體電路技術發展中最重要的課題。 首先，本論文介紹目前關於超薄氧化層可靠度方面的研究重點，包括：穿隧漏電流(tunneling current)、氧化層厚度的決定、氧化層依時崩潰特性(TDDB)、軟性崩潰(soft breakdown)及其對元件之影響、溫度效應，應力極性(stress polarity)對氧化層崩潰的影響以及評估超薄閘極氧化層的方法等問題及其相互間的關係，都將詳細探討並與已發表之論文比較之。 其次，我們研究電漿充電損害效應對超薄閘氧化層元件的影響。利用一下吹式光阻灰化機台(down stream plasma asher)探討其所產生之天線效應對不同氧化層厚度之元件所造成的影響。我們發現電漿充電損害(plasma charging damage)仍然會造成超薄氧化層在可靠度方面的嚴重退化，而且製程的溫度與電漿環境的電位極性扮演著重要的角色。同時發現當閘極氧化層厚度降低到4nm以下之後，傳統上用電晶體參數以評估電漿充電損害的指標，諸如臨限電壓(threshold Voltage)，相對電導(transconductance)，次臨界波動(subthreshold swing)等，將不再適用於電漿充電損害的偵測上，而崩潰電荷法(charge-to-breakdown, Qbd)，電應力導致漏電法(stress-induced leakage current, SILC)將可應用於超薄氧化層元件之電漿充電損害的指標。另外我們比較P型元件與N型元件之充電損害效應後發現，由於對充電極性之敏感度不同，P型元件對充電損害的免疫力遠較N型元件為差，我們深入探討此一現象並以N型及P型元件之崩潰電荷極性與本質穿隧電流極性上的差異來解釋。 再則，我們藉由離子佈植方式將氟與氮原子植入矽基底及多晶矽的方式成長氮化及氟化氧化層，同時也以N2O成長氮化氧化層，以研究氟化及氮化氧化層之可靠度，首先我們發現以搭配基底植入氮及氟離子的方式可以成長多重厚度的氧化層(multiple oxide thickness)，然而其效果在N2O氧化層將較不明顯，此技術可以適用於未來單晶片系統(system-on-chip, SOC)中達成在同一晶片上成長不同厚度的閘氧化層，以配合不同電路元件應用的需要。其次我們發現N2O氮化氧化層可有效地改善閘氧化層的可靠度，尤其是在抗電漿充電損害上可明顯地抑制充電導致的漏電流，此效應在P型元件上最為顯著。另外，藉由同時植入適量的氟與氮原子，幾乎可完全抑制電漿損害，而對N2O氧化層而言，單獨植入適量的氟可達到最佳效果，我們提出可能的機制來說明此一改善的現象。最後雖然氟原子因會加速硼穿透，故無法在P型元件中應用。經我們研究後發現適量的氟摻雜，不僅沒有惡化硼穿透且可改善P型元件之氧化層可靠度，故氟化與氮化氧化層技術可適用於互補式金氧半(CMOS)元件應用。 另外，我們研究超薄氧化層元件之製程導致氧化層退化效應，包括：多晶矽閘極摻雜(polysilicon doping)、硼穿透(boron penetration)及電漿充電與蝕刻損害(plasma charging and etching damage)對超薄氧化層元件之影響。我們發現雖然氧化層崩潰特性隨閘極摻雜濃度提高而改善，但電漿充電損害效應卻隨之惡化，其機制也提出探討。我們也研究評估硼穿透效應對超薄氧化層元件的影響，特別是其對P型元件天線效應的關係，同時提出一種提昇P型元件抵抗硼穿透的製程方式。最後我們評估電漿蝕刻損害效應後發現，蝕刻損害效應不易由傳統的電性量測方式偵測出來，然而潛在的蝕刻損害卻會加速惡化後續的充電損害，造成閘極氧化層可靠度更嚴重的退化。 由於多晶矽空乏(poly depletion)效應造成元件特性的退化，回歸金屬閘極(metal gate)結構似乎無法避免，然而金屬閘極元件的製程本身卻也帶來許多問題，特別是由於較多的電漿製程的使用所造成的損害及後續無法以高溫製程退火(annealing)。我們研究以濺鍍氮化鈦(sputtered TiN)為金屬閘極元件之電漿損害效應後發現，閘極氧化層會因濺鍍損害及與金屬介面反應而降低其有效厚度，此外氧化層可靠度與後續的退火處理條件有很大的相關。而金屬閘極元件的可靠度相較於傳統多晶矽閘極元件差，漏電流增加，崩潰電荷(Qbd)降低，特別是電漿充電抵抗的嚴重退化，即使是採用N2O氮化氧化層亦然。最後我們以電漿化學氣相沉積(PECVD)機台低溫退火後可有效地改善金屬閘極元件之氧化層可靠度。 最後我們提出一修正之滲透模型(modified percolation model)來解釋超薄氧化層之退化及崩潰現象。首先藉由觀察氧化層崩潰後特性發現崩潰位置對元件崩潰後特性有決定性的影響。故崩潰點位置可由崩潰後特性看出，我們並由光子發射(photo-emission)顯微鏡觀察證實。再則我們發現超薄氧化層在硬性崩潰(hard breakdown)與軟性崩潰外的一種新的崩潰型式，我們稱之為部份崩潰(partial breakdown)，並提出一修正之滲透模型來解釋其相關現象。最後，我們觀察到超薄氧化層電流之本質負電阻(negative differential resistance)現象，並提出一種新穎的量測方法來偵測MOS結構中多晶矽閘極與氧化層之介面陷阱(interface trap)，藉此可以定性及定量評估閘極氧化層及介面陷阱的形式。

Ultrathin gate oxide, which is essential for low supply voltage and high driving capability, is indispensable for the continued scaling of ULSI technologies towards smaller and faster devices. Needless to say, the reliability of ultrathin oxide is of major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. In this thesis, the reliability issues regarding ultrathin gate oxide for present and future ULSI technologies are extensively investigated and discussed. Firstly, we start with a review of the present understanding of general reliability issues, their mutual relationship, effects on gate oxide integrity (GOI) and the consequences for oxide thickness scaling. Issues relating quantum mechanical tunneling current, determination of ultrathin oxide thickness, time-dependent dielectric breakdown characteristics, characteristics of soft-breakdown and its impacts on device reliability, effects of temperature, stressing polarity and oxide thickness dependences of ultrathin oxide breakdown, and evaluation of ultrathin oxide reliability is comprehensively demonstrated. Secondly, plasma-induced charging damage in thin gate oxides with thickness ranging from 8.7 to 2.5 nm is investigated and analyzed by subjecting antenna devices to a photoresist ashing step after metal pad definition. Oxide thickness dependence of charging damage is discussed and the evaluation of charging damage in ultrathin gate oxides (Tox < 4 nm) is also demonstrated. The charging damage characteristics induced in nMOS and pMOS devices are also compared. Our experimental results show that pMOS devices are more sensitive to plasma charging and more susceptible to positive charging damage. Possible mechanism responsible for these phenomena is also discussed. Thirdly, the effects of fluorine and nitrogen incorporation on ultrathin gate oxide integrity (GOI) are investigated by introducing N2O-nitrided oxide as gate dielectric and by implanting fluorine and nitrogen into poly gate or Si substrate. Multiple oxide thickness, which is essential for achieving system-on-a-chip (SOC) technology, by fluorine and nitrogen implant, is first introduced. Improved immunity of plasma charging damage in nitrided oxide and fluorinated oxide is then investigated. It is observed that charging damage can be significantly suppressed for nitrided oxide and fluorinated oxide. Finally, improved CMOS GOI, even for p-channel devices, is actually achieved for the first time with medium-dose fluorine implantation, without causing noticeably worsened boron penetration. Process-induced oxide degradation in ultrathin gate oxides is then presented. Issues including effects of polysilicon doping concentration, boron penetration, and polysilicon etching damage on ultrathin oxide reliability are investigated comprehensively. We found that while oxide reliability shows a noticeable improvement with increasing doping concentration, plasma-induced charging damage is actually aggravated with increasing doping concentration. Effects of boron penetration on device characteristics and its impacts on charging damage are also discussed. Finally, plasma etching-induced damage is investigated by subjecting various devices to TCP (Transform Coupled Plasma) poly etcher (e.g., LAM TCP 9400) with different over-etching durations. Gate oxides and poly re-oxidation are thermally grown in either pure O2 or N2O ambient in order to compare the damage in various oxides. Followed by a comprehensive study on the plasma process induced damage in sputtered TiN metal-gate capacitors with 4nm N2O-nitrided oxide. A significant reduction in the effective oxide thickness extracted from C-V measurement is observed for the metal-gated devices. The effects of post-deposition RTA temperature on the flat-band voltage (Vfb) and interface state density (Dit) are studied. In addition, charging damage due to the additional plasma processes in metal gate process flow is analyzed. Finally, post-metal plasma treatments are studied for suppressing the gate leakage current of metal-gate devices. Finally, a modified percolation model for ultrathin gate oxide breakdown is proposed. We start with investigating the post-breakdown characteristics of ultra-thin oxides. The pre- and post-breakdown characteristics of MOS devices are compared and a strong dependence on the breakdown spot locations is observed. The location of breakdown spot can be identified according to post-breakdown drain current characteristics and further verified by the photo-emission analysis. In order to find some clues for explaining the evolution and different stages of oxide degradation, effects of oxide breakdown on device's characteristics are investigated in detail. In addition to the well-known soft-breakdown and hard-breakdown, a new breakdown mode, which we named as "partial breakdown" (PBD), is observed and identified. The corresponding physical origin and mechanism are then demonstrated. Accordingly, a new technique for probing the intrinsic traps near the gate/oxide interface of MOS structure is proposed. Effects of nitridation and fluorination on oxide breakdown are also compared and discussed. Introduction 1.1 Overview of Ultrathin Oxide Reliability 1 1.2 Process-Related Oxide Reliability 3 1.3 Organization of the Thesis 4 References 7 Chapter 2 Reliability of Ultrathin Gate Oxides for ULSI Devices 2.1 Backgrounds and Motivation 13 2.2 Gate Leakage Current 14 2.2.1 Quantum Mechanical Tunneling 14 2.2.2 Determination of Ultrathin Oxide Thickness 16 2.2.3 Alternative Gate Dielectrics 18 2.3 Breakdown Characteristics 19 2.3.1 Occurrence of Soft-Breakdown 19 2.3.2 Oxide Thickness Dependence and Polarity Dependence 21 2.3.3 Influence of Oxide Breakdown on Device Operation 23 2.4 Temperature-Accelerated Dielectric Breakdown in Utrathin Gate Oxides 25 2.4.1 Oxide Thickness Dependence 25 2.4.2 Nitridation Effects 29 2.5 Evaluation of Ultrathin Oxide Reliability 29 2.5.1 Time-Dependent Dielectric Breakdown 29 2.5.2 Hot-Carrier Reliability 30 2.6 Conclusion 31 References 33 Chapter 3 Plasma-Induced Charging Damage in Ultrathin Gate Oxides 3.1 Backgrounds and Motivation 66 3.2 Experimental 68 3.3 Charging Damage Induced During Plasma Ashing 69 3.3.1 Occurrence of Charging Damage During PR Ashing 69 3.3.2 Oxide Thickness Dependence of Plasma Charging Damage 70 3.4 Evaluation of Charging Damage in Ultrathin Gate Oxides 71 3.5 Plasma Charging Damage in NMOS and PMOS Devices 74 3.5.1 Threshold Voltage Measurement 74 3.5.2 Charge-to-Breakdown Measurement 75 3.5.3 Gate Leakage Current Measurement 76 3.6 Conclusion 77 References 79 Chapter 4 Improved Immunity to Plasma Induced Charging Damage in Ultrathin Nitrided and Flourinated Oxides 4.1 Backgrounds and Motivation 102 4.1.1 Nitrogen Engineering in CMOS Technology 103 4.1.2 Fluorine Engineering in CMOS Technology 104 4.1.3 Multiple Oxide Thickness for Fluorine and Nitrogen Implantation 105 4.2 Experimental 106 4.3 Improved Immunity of Charging Damage in N2O-Nitrided Oxides 107 4.3.1 Suppression of Gate Leakage Current Caused by Charging Damage in Nitrided Oxides 108 4.3.2 Improved Temperature-Accelerated Oxide Degradation in Nitrided Oxides 108 4.4 Plasma Charging Damage in Fluorine- and Nitrogen- Implanted Oxides 109 4.5 Re-examination of Improved Immunity to Plasma Damage in Fluorinated and Nitrided Oxides 111 4.6 Improved Gate Oxide Integrity in PMOS with Fluorine Implantation 113 4.7 Conclusion 116 References 117 Chapter 5 Process-Induced Oxide Degradation in Ultrathin Gate Oxides 5.1 Backgrounds and Motivation 143 5.2 Experimental 145 5.3 Effects of Polysilicon Doping Concentration on Ultrathin Oxide Reliability 146 5.3.1 Basic Characteristics 147 5.3.2 Effects of Doping Concentration on Gate Oxide Breakdown Characteristics 149 5.3.3 Effects of Doping Concentration on Charging Damage 151 5.4 Boron Penetration in Ultrathin Gate Oxides 152 5.4.1 Effects of Boron Penetration on Device Characteristics 153 5.4.2 Methods to Eliminate Boron Penetration 154 5.4.3 Effects of Boron Penetration on Charging Damage 156 5.5 Plasma Etching Damage in Ultrathin Gate Oxides 157 5.6 Conclusion 159 References 161 Chapter 6 Plasma Process-Induced Damage in Sputtered TiN Metal Gate Devices 6.1 Backgrounds and Motivation 194 6.2 Experimental 195 6.3 Basic Characteristics of TiN Metal Gate Oxide Device 196 6.4 Plasma damage in Devices with TiN Metal Gate 197 6.5 Suppression of Plasma Damage by Plasma Annealing 198 6.6 Summery 199 References 200 Chapter 7 A Modified Percolation Model for Ultrathin Oxide Breakdown 7.1 Backgrounds and Motivation 215 7.2 Oxide Breakdown Modes and its Characteristics 216 7.3 A Modified Percolation Model 219 7.3.1 Introduction 219 7.3.2 Experimental 219 7.3.3 Results 220 7.3.4 The Breakdown Model and Discussion 221 7.4 A New Breakdown Mode and its Evolution in Ultrathin Gate Oxides 222 7.4.1 Introduction 223 7.4.2 Negative Differential Resistive (NDR) Characteristics 224 7.4.3 The Mechanism 224 7.5 Conclusion 226 References 228 Chapter 8 Conclusions and Suggestions for Future Work 8.1 Contributions of this Study 245 8.2 Suggestions for Future Work 248