一種用於低功率及高效率快閃式記憶體之新型寫入方式

Abstract

快閃式記憶體(Flash Memory)於近幾年來已為非揮發性記憶體產品之主流。就一個先進的快閃式記憶元件設計來說，高效能(Performance)與高可靠性(Reliability)是兩個主要的考量重點。快閃式記憶體的設計改良主要可區分為改善元件結構及改變操作方式兩大方向，而最直接且有效的方法並可立即應用於現有成熟製程技術中，則以改變操作方式可達到較佳的效能。 本論文中，吾人提出一種用於低功率及高效能快閃式記憶體的新式寫入方式，即是利用基極偏壓增強汲極累增崩潰熱電子注入(Substrate Bias Enhanced Drain Avalanche Hot-Electron Injection, SBAHE)達成寫入操作。實驗結果顯示，以此寫入方式操作，其寫入速度提高及功率損耗降低，有良好的元件效能表現；而在元件可靠性方面，則可減少對氧化層的傷害，尤其對介面狀態(Interface State, Nit)的壓抑。同時，我們也將此一新的操作方式與目前最廣泛使用的通道熱電子注入(Channel Hot-Electron Injection)方式比較，結果顯示新的方法無論在元件效能或可靠性方面都有較為優異。此外，吾人亦藉由元件模擬，提出一最佳化元件結構。根據模擬結果顯示，以此新式寫入方式操作於此最佳化結構中，將可同時大幅提升記憶元件之效能與可靠性。因此，藉由實際元件之測量與模擬結果之預測，此一新式寫入方式與最佳化結構，將可應用於下一世代高操作效能與高可靠性的快閃式記憶體中。

Recently, the flash memory has become the main stream of nonvolatile semiconductor memory products. For the design of advanced flash memories, the performance and reliability are the major concerns. The design and improvement of flash memories are mainly focused on two approaches, one is to develop a novel cell structure, and the other one is to develop a different operation scheme. The most effective way to improve the cell performance and reliability is by way of a different operation scheme which can be fitted into a matured cell technology. In this thesis, we proposed a new write operation scheme for low power and high efficiency flash memory application. The provided new scheme is called the Substrate Bias Enhanced Drain Avalanche Hot-Electron (SBAHE) Injection. From the experimental results, this new scheme has high speed and low power features. In addition, in the terms of cell reliability, the oxide damage can be suppressed. Especially, the interface state generation can be inhibited. In the meantime, we compare the results of new scheme with those of widely used channel hot-electron (CHE) scheme. The new scheme exhibits much better performance and reliability than those of CHE scheme. Furthermore, the 2-D device simulation was performed. An optimum cell structure is obtained for the SBAHE injection scheme. From the simulated results, the cell performance and reliability can be significantly improved with this new write scheme and the optimized cell structure. Therefore, the new scheme along with the optimized cell structure is well-suited for the next generation high performance and high reliability flash memory applications. Chapter 2 The Substrate Bias Enhanced Drain Avalanche Hot-Electron Injection Mechanism Chapter 3 Device Fabrication and Experimental Measurements Chapter 4 Results and Discussion Chapter 5 Design of An Optimized Cell Structure Chapter 6 Conclusion