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dc.contributor.author盧思維en_US
dc.contributor.authorSzu-Wei Luen_US
dc.contributor.author楊宗哲en_US
dc.contributor.authorTzong-Jer Yangen_US
dc.date.accessioned2014-12-12T02:23:24Z-
dc.date.available2014-12-12T02:23:24Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880429040en_US
dc.identifier.urihttp://hdl.handle.net/11536/65830-
dc.description.abstract摘要 本文主要的目的是以實驗的方式探討複層式填充物在覆晶技術中製程的可行性。 傳統的覆晶技術為先在晶圓上進行植球,再組裝於基板,最後進行填膠作業。但由於晶圓為高價位之產品,植球過程中容易產生風險; 再者傳統填膠之熱膨脹係數(CTE)與Si及基板者差異頗大,容易造成封裝的可靠性問題。 本研究為驗證一新型覆晶技術以突破上述困擾。 概念為於價位較晶圓低之基板上進行植球,並使用兩種不同之材料填膠,其中第一層填膠之CTE與基板接近,而第二層填膠則與Si接近,以漸層之方式減緩CTE不匹配之現象。本研究除成功的驗證上述技術之可行性外,並於研究過程中順利針對若干製程問題點提出解決方案。zh_TW
dc.description.abstractThe feasibility of solder columns with stratified underfill technology is explored in this study. In traditional flip chip technology, solder bumps are first deposited on the die, assembled with substrate and then filled with a underfill. However, in the bumping process, there exists a high risk of damaging the wafer which reduces the yield and increases cost. In addition, the significant CTE mismatch between die and substrate also generates the reliability issue after the assembly process. In order to overcome the above problems, in this study, a new concept named “Stratified Underfilling Flip Chip Technology” is proposed and explored. In this new method, two underfills with different CTEs are used to eliminate the CTE mismatch problem. The CTE of the underfill next to the Si side, CTE is similar to that of Si. On the other hand, the CTE of the underfill next to the substrate side is compatible to that of the substrate. Besides the feasibility study of this new concept, solutions to many process issues, such as incompatibility of polyimide and electroless Ni/Au process are also proposed.en_US
dc.language.isozh_TWen_US
dc.subject覆晶技術zh_TW
dc.subject複層式填充物zh_TW
dc.subject熱膨脹係數zh_TW
dc.subject封裝技術zh_TW
dc.subject電鍍zh_TW
dc.subject錫鉛凸塊zh_TW
dc.subject無電鍍zh_TW
dc.subject組裝製程zh_TW
dc.title複層式填充物在覆晶技術中製程之探討zh_TW
dc.titleThe Study of Stratified Underfills Process In Flip Chip Technologyen_US
dc.typeThesisen_US
dc.contributor.department電子物理系所zh_TW
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