基於心臟收縮陣列之RBF類神經網路VLSI設計

Abstract

類神經網路在許多實際應用中有很好的效果，例如語音辨識、圖形識別等。一般類神經網路的實現方法是在電腦上以軟體模擬來進行，但類神經網路通常含有大量的平行運算，以軟體方式進行無法達到即時的要求，因此若能以超大型積體電路（VLSI）直接實現，將可達速度上的要求。 在本論文中，我們將使用超大型積體電路技術來實現放射狀基礎網路函數。具體電路架構則以心臟收縮式陣列(systolic array)完成，並將資料路徑予以三級管線化以增快處理速度。類神經網路在不同應用中所需之各層神經原個數不盡相同，因此本論文提出一個基本處理單元(Basic Module)，然後利用此單元的重複使用以應付各種可能的神經原個數。最後將整個架構運用於一個模糊歸屬函數的映射例子中來證明其功能。

Significant potential exists there for parallel processing and implementation in ANN realizations. Among the existing and well understood parallel architectures, systolic processor arrays stand out as a natural selection for neural network implementations. This thesis describes a systolic neural network architecture for implementing the radial basis function (RBF) neural model. Because the numbers of nodes in each layer of ANN vary from one application to another, a 4x4x4 modular network is proposed as the standard building block module to realize all kinds of RBF neural structure. Finally we use the proposed processor array to realize a 7 to 3 fuzzy membership function mapping, and demonstrate its performance. CONTENTS I LIST OF TABLES IV LIST OF TABLES VI CHAPTER 1. INTRODUCTION 1 1.1. MOTIVATION 1 1.2. THESIS ORGANIZATION 3 CHAPTER 2. RBF NEURAL NETWORKS 4 2.1. RBF NETWORK STRUCTURE 4 2.2. RBF UNIT CHARACTERISTICS 5 2.3. BASIS FUNCTION INTERPRETATION 6 2.4. RBF NETWORK DESIGN AND TRAINING 6 2.4.1. c-Means Algorithms 7 2.5. RBF APPLICATIONS 8 CHAPTER 3. THE VLSI ARCHITECTURE OF RBFNN 9 3.1. DESIGN FLOW 9 3.1.1. Hardware Description Language (HDL) 13 3.1.2. Logic Synthesis 14 3.1.3. Logic Simulation 15 3.1.4. Physical Design and Verification 15 3.2. A 4X4X4 RBFNN 17 3.2.1. Mapping RBF Algorithms to Systolic Arrays 17 3.2.2. Deriving DGs from Algorithms 18 3.2.3. Mapping DGs onto Array Structures 19 3.2.4. Ring Systolic Design 22 3.2.5. Ring Systolic Processing for the Retrieving Phase 23 3.2.6. Detailed PE Design 25 3.3. THE RBFNN ARCHITECTURE 27 3.3.1. Specification 27 3.3.2. System Overview 27 3.3.3. Architecture 27 3.3.4. Arithmetic Unit 29 3.3.5. Control Unit 37 3.3.6. Mapping ANN onto the Designed 4x4x4 Basic Unit 42 CHAPTER 4. SIMULATION 44 4.1. ANALYSIS 44 4.2. MEMBERSHIP FUNCTION MAPPING SIMULATION 46 CHAPTER 5. CONCLUSION AND FUTURE WORK 49 5.1. CONCLUSION 49 5.2. FUTURE WORK 49 REFERENCES 51