數據通訊用PIN diode之高速特性

Abstract

本篇論文主要針對PIN diode之小訊號等效電路模擬、封裝效應，及其高速特性作探討。以PIN diode的物理結構為基礎，說明典型的PIN diode小訊號等效模型；藉由引入distributed RC effect觀念所得到之電路模型，可以得到更好的參數萃取結果；再考慮擴散濃度分布的影響下 ，我們得到一個Rd及Cd之修正等效電路模型，利用此修正之等效電路架構，可以讓最佳化參數之萃取的誤差在1%之內。另外，對於現今常用在光電元件上的TO-can封裝型式，我們嘗試用最簡易的方式去定義它，就整個封裝可能所造成的效應加以探究，同時以實驗的方式去得知TO-can封裝在高速操作下的限制。而對於Hybrid PIN-FET，我們也顯示出其高速特性。

The small signal equivalent circuit, packaging effects and high-speed characteristics of the PIN diode are investigated in this thesis. We demonstrate a typical small signal equivalent circuit of the PIN diode based on the device physics. By introducing the concept of a distributed RC effect into the model, we can obtain better extracting circuit parameters. As a result, the error of the optimization extracting parameters can be within 1%. In addition, for the TO-can package which is commonly used nowadays, we tentatively use a rough circuit model to define it and investigate the possible effects. The experiments exhibit the limit of TO-can package under high-speed operation. The high-speed characteristics of the hybrid PIN-FET are also presented.