高介電氧化層MOSFET元件之低漏電電荷幫浦量測技術

Abstract

當元件氧化層持續微縮時，以二氧化矽為基底做為CMOS元件的氧化層會有其物理極限上的限制，故以高介電係數材料當作元件氧化層是一個重要的課題。然而，除了移動率降低與臨界電壓漂移的問題之外，因為高介電係數氧化層本身具有相當多的缺陷，造成電荷快速的捕捉與釋放，而形成臨界電壓的不穩定亦是另一個可靠性的問題。所以，發展一套簡單、快速且適用於高介電係數氧化層結構的方法去分析電荷捕捉的特性顯得相當重要。而不僅僅是使用高介電係數氧化層，利用環狀離子佈植去改善短通道效應也是不可或缺的。然而，不同的環狀離子佈植也會造成元件不同的退化情形。

本論文將著重在利用差頻電荷幫浦法(IFCP, Incremental Frequency Charge Pumping)去分析90奈米N型高介電係數氧化層MOSFET元件。我們結合IFCP方法和陷阱到矽基板傳導帶的穿遂時間常數來得知缺陷在高介電係數氧化層的位置。一開始，透過這個量測方法，我們可以發現缺陷的產生和閘極偏壓的條件有相當密切的關係。在基板注入時，它對高介電係數氧化層造成的傷害較大，而介面傷害程度較大是發生在閘極注入。

在本文的後半，對於N通道MOSFET元件，我們透過高溫正偏壓的操作下來加速元件的衰退現象。由於高溫正偏壓不穩定性的測試對於使用環狀離子植入製程所成的邊緣傷害並不明顯，所以，我們利用高溫時的熱載子效應測試，來有效的觀測閘極邊緣傷害的程度。藉由實驗的結果，我們可以發現藉由較大質量環狀離子佈植，它臨界電壓的不穩性或介面陷阱的產生會來的比較少。

The aggressive scaling of CMOS devices has driven SiO2-based gate dielectrics to its physical limits, as a result, high-K materials as a gate stack has attracted a lot of interests. However, apart from mobility degradation and threshold voltage (VT) shifts, VT instability caused by trapping and detrapping of pre-existing defects is another reliability concern. Therefore, it becomes important to develop a simple and fast method to quantitatively characterize charge traps in high-k dielectrics. Not only high K gate stack is needed, but also halo implant process with short channel effect control is inevitable. However, various degradations of the devices with different halo implant species incurred.

This thesis has been focused on utilizing IFCP(Incremental Frequency Charge Pumping) method for the measurement of high gate dielectrics 90nm nMOSFET's. By combining IFCP method and trap-to-band tunneling time constant, the calculation of trap position in the HfSiON has been implemented. By using this technique, it was found that the correlation between trap generate and stress polarity dependence can be identified. It causes more serious damage in HfSiON during substrate injection. While, during gate injection, it induces more traps in the Si/IL (interfacial layer) interface.

We have also studied the n-MOSFET device degradation through PBTI(Positive Bias Temperature Instability) stress in the later half of this thesis. Since PBTI is not a sensitive test to distinguish the effect of different halo implant species from the gate edge, PBTI-like stress has been employed to provide an understanding of the degradation at the gate edge. From the experimental results, we can find that the VT instability and interface trap generation are suppressed in the n-MOSFET's with heaviest halo implant species.