鈷與矽鍺的反應機制與研究

Abstract

在本論文當中,我們以超高真空化學分子束磊晶系統成長單晶矽與矽鍺磊晶層,並且以室溫及高溫等不同溫度來濺鍍鈷金屬與單晶矽鍺反應,在反應的過程中,以鍺比例居多的矽鍺析出物及鈷與矽鍺的三元反應,可由掃描式電子顯微鏡與X光繞射發現,並且分析比較不同的鍺含量、濺鍍方式還有結構改變的情況下,鍺在析出物以及三元反應中比例的變化;除此之外,由高能X光繞設的結果可以得知,高溫濺鍍可以減緩矽鍺晶格鬆脫的程度。我們嘗試用一種簡單的原理來解釋這些現象。而且對於高溫濺鍍中高比例的者原子及無依循基板方向的特性等，提出在金屬矽化反應中鈷－矽－鍺混合區的反應。 利用超高真空化學分子數選擇性磊晶成長的技術，製作硼摻雜矽鍺淺接面正負接面，以期能應用於矽鍺磊晶源/汲極金氧半電晶體之源件運用上，藉著漏電流的分析，擷取二極體接面最佳化的條件。並藉由不同的退火條件中，得到較佳的接觸電阻與片電阻值。 基於這些特質及優點，再加上不複雜的新製程整合步驟，不需另加光罩或黃光程序，使得此新結構在未來的至發展上更具潛力。

As the transistors continue to scale down, the characteristics of Co/Si1-xGex junction have received lots of attention because of its potential applications to heterojunction bipolar transistors. Among the potential metal silicides, CoSi2 is particularly attractive for its low resistivity, cubic structure relatively small lattice mismatch with Si, and its compatibility with self-aligned silicide(SALICIDE) scheme. We have fabricated Co/Si1-xGex junction using room-temperature and high-temperature (i.e., at 4500C) sputtered Co on top of strained Si0.86Ge0.14 and Si0.91Ge0.09 layers prepared by ultra high vacuum chemical molecular epitaxy (UHVCME). The relative composition of Ge in Ge-rich Si1-zGez precipitate and the solid solution of ternary phase silicide of Co-Si-Ge system were compared between room-temperature and high-temperature sputtered samples. We found that the high-temperature-sputtered samples are more effective in inhibiting lattice relaxation, which would be beneficial for manufacturing metal silicide/Si1-xGex structure devices. Mechanisms were proposed to explain the large difference between the room-temperature and high-temperature sputtered samples. It is believed that the mixed Co-Si-Ge solution on high-lemperature-sputtered samples is responsible for the different silicidation behaviors. Strained boron-doped Si1-xGex, layers with different Ge mole fractions were selectively deposited by ultra high vacuum chemical molecular epitaxy (UHVCME) to form shallow p+-n junction suitable for raised source/drain metal oxide semiconductor field effect transistor (MOSFET) applications. Detailed electrical characterizations were performed. Our result show that the reverse leakage current could be optimized by a rapid thermal annealing RTA at 9500C for 20 seconds, and a near perfect forward ideality factor (i.e. < 1.01) is obtained for the p+-n Si1-xGex/Si junction. By analyzing the periphery and area leakage current components of p+-n Si1-xGex/Si junctions with various perimeter lengths and areas, the degree of misfit dislocations and undercut effect were studied. The specific contact resistance was found to decrease as Ge mole fraction increases. Junction depth measurements also show that the junction depth decreases monotonically with increasing Ge mole fraction.