具有信號處理能力的嵌入式微處理器之指令集設計及解碼器實作

Abstract

後PC時代的興起，帶動資訊家電市場的新應用需求。對於多媒體、通訊、以及消費性電子產業有殷切整合的必要。將來嵌入式微處理機器與數位信號處理器的使用範圍將持續擴大，包括傳統的數據機、VoIP、手機和個人數位助理之無線通訊應用；以及影音技術方面有關的編解碼器與訊號轉換方式。這些應用都同時包含『控制』和『數位訊號處理』的功能。過去是分別使用微處理器和數位訊號處理器來設計系統，此舉不但造成作業系統和發展工具之複雜度；更大大增加整體面積和兩處理器之間的時間預算，產生成本不符經濟效益的情況。新世代的數位訊號微處理器集兩者大成於一身，即在傳統RISC架構下的嵌入式微處理器中帶入多功能之數位訊號處理能力指令。 因此，本篇論文由ARM9E-S研究出發，發展具有信號能力的嵌入式微處理器之指令集。從下列三個方向著手。一、刪除每個指令的條件執行碼，以期在數位訊號處理方面之應用有較高的效能；另一方面，此舉亦為一迴避專利之設計。二、將四層的解碼樹減少至一層。三、詳細分門別類各指令歸屬。當然，文中亦說明本指令集在各應用領域的效能分析。 最後，落實本指令集之設計至本嵌入式微處理器之解碼器。我們採用Verilog硬體描述語言來實作，並於文末詳細指出其與相關模組之介面與溝通模式。

Applications in telecommunication or multimedia require a new generation of fast and flexible microprocessors. A novel 32-bit hybrid RISC/DSP microprocessor is presented with RISC architecture and extended functionality for digital signal processing. This unifying of RISC and DSP was not designed by simply combining a general-purpose microprocessor and a DSP core, but a new concept for the implementation of DSP processors. With the architecture presented it has been proven that a DSP processor will achieve high performance under RISC philosophy with DSP capable instruction set. Following the perception described above, we survey from ARM9E-S with ARM V5TE architecture and then present a 32-bit instruction set in this paper. Three significant issues are taken into consideration while reconfiguring the instruction set. First, take off condition codes for higher performance under DSP purpose applications and avoiding the claims of the patent. Second, reduce decoding level from four to one. Third, separate each instruction category clearly with loose encoding format embedded. There is also provided performance evaluation proving the advantages of our instruction set. Finally we verify the design of the instruction set by implementation of the decoder using Verilog language. Of course, we also show the interface between each functional block in detail supplying handshaking strategy.