利用電源閘與互斥或邏輯閘保持器技術之高能源效應內容可定址記憶體電路設計

Abstract

本論文利用電源閘與互斥或邏輯閘保持器的技術，可以大量降低內容可定址記憶體之靜態與動態的功率消耗。由於CMOS製程已經進步到深次微米甚至奈米的時代，漏電流的問題也隨著臨界電壓及元件尺寸的降低而日益嚴重。一個應用電源閘技術的64行×32位元內容可定址記憶體，利用TSMC 100nm CMOS技術加以實現，由模擬結果顯示利用此技術可減少12％的動態功率及35％的靜態功率消耗且沒有造成任何搜尋時間的增加。另外，對於64行×32位元的內容可定址記憶體，應用電源閘的技術大約會增加7.8％的額外面積。

利用互斥或邏輯閘的條件式保持器的技術，本篇論文提出了一個全新抗雜訊比對線電路。利用互斥或邏輯閘的控制電路，在運算相位時即關掉保持器，藉此可以避免多餘的功率消耗及減少搜尋比對的時間。應用此技術，亦可降低比對線上之比對電路的元件尺寸，以達到減少比對線上負載的目的。一個高能源效應的256行×128位元三元內容可定址記憶體亦被提出，利用TSMC 0.13μm CMOS 技術來實現電路設計與佈局。根據模擬結果顯示，此新的三元內容可定址記憶體可以減少37.8％的搜尋比對時間及15.6％的動態功率消耗。

The low-power content-addressable memories (CAMs) using power-gating and XOR-based conditional keepers techniques are realized in this thesis. As the technology scale down to deep-submicron and nano-scale eras, the leakage current becomes more serious due to lower threshold voltage and smaller size of transistor devices. Applying power-gating techniques to 64-word x 32-bit CAM is implemented in TSMC 100nm CMOS technology. According to simulation results, the proposed CAM achieves 12% dynamic power reduction and 35% static power consumption and it doesn’t cause any search time overhead. However, for 64-word x 32-bit CAM array, 7.8% area overhead is caused by power-gating devices. A novel noise-tolerant match-line scheme which applies the XOR-based conditional keeper techniques is proposed in this thesis. Based on the XOR-gate controller signal, the keeper would be turned off at the beginning of the evaluation phase. Accordingly, the proposed match-line scheme not only saves search power but also reduces the search time. In addition, if the XOR-based conditional keepers are applied, the smaller size of comparison circuit would be required to reduce the match-line loading at the same search time criteria. A 256-word x 128-bit energy-efficient ternary CAM is also proposed and simulations and layout are implemented in TSMC 0.13μm CMOS technology. Simulation results show that 37.8% search time reduction and 15.6% dynamic power saving are achieved by proposed ternary CAM.