標題: | 應用於大鄰近層細胞類神經網路通用機器之新型互補式金氧半細胞架構 A New CMOS Large-Neighborhood Cellular-Neural-Network (CNN) Cell Structure For Large-Neighborhood CNN Universal Machine (CNNUM) |
作者: | 蕭喬蔚 Chiao-Wei Hsiao 吳重雨 Chung-Yu Wu 電子研究所 |
關鍵字: | 細胞神經網路;通用機器;大鄰近層;Cellular Neural Network;Universal Machine;Large Neighborhood |
公開日期: | 2000 |
摘要: | 在這篇論文中,一個新型可以超大型積體電路實現的大鄰近層細胞神經網路被提出以及分析。在提出的架構中,寄生的雙載子接面電晶體被使用在神經細胞以及神經腱結之中。從原件物理出發,這一個新的神經細胞架構是很精簡的,而且已經被提出及分析。除此之外,因為新架構同時使用了NPN及PNP的雙載子接面電晶體,對個低功率消耗的神經腱結架構已設計出來。
奠基於大鄰近層細胞神經網路的理論,大於兩鄰近層以上的權重模板是可以在不加上多餘的複雜連線下以超大型積體電路實現。所以晶片的面積可以被縮減,而且陣列大小也可以提高。使用所提出的新架構,諸如「Muller-Lyer」箭頭模糊化以及連結物件偵測器等等的功能,皆已成功地在HSPICE下模擬驗證。一個16 X 16的大鄰近層細胞神經網路,其面積為1200微米乘以2580微米,已在台積電0.25微米製程下製做完成。全部的功率消耗為50mW。
最後,大鄰近層通用機器亦被提出。使用了大鄰近層細胞神經網路做為核心計算單元,這一個類比訊號處理器已經被實現。
從以上的結果可知,這一個被提出的大鄰近層細胞神經網路在硬體實現這個應用於多樣訊號處理的通用機器上有很大的潛力。在這個領域中將有更多的研究努力投注。 In this thesis, a new structure for the VLSI implementation of large- neighborhood cellular neural network (LN-CNN) is proposed and analyzed. In the proposed LN-CNN structure, the parasitic lateral bipolar junction transistor (BJT) in the CMOS process is used to implement both the neuron and synaptic path. Based on the basic device physics of the neuron-BJT (νBJT), a new compact neuron structure is proposed and analyzed. Besides, because of using NPN and PNP BJTs together, a low-power structure of synaptic path is designed and verified. The new low power is composed of dual path for positive or negative current flow in. There is no DC standby current, and it consumes no DC power. Basing on the concept of LN-CNN, the templates with more than two neighborhood layers can be realized without extra complex connections in VLSI implementation. So the chip area for interconnections is reduced and the array size could be increased. The above mentioned low power synaptic path circuit is used, so the LN-CNN is a lower power design. Using the proposed LN-CNN structure, the LN-CNN functions such as Muller-lyer arrowhead illusion and connected component detector, have been successfully realized and verified in HSPICE simulation. Both the negative and the asymmetrical template can be realized. A 16 X 16 LN-CNN with chip area 1200μm X 2580μm is designed and fabricated by 0.25μm TSMC 1P5M CMOS process. The total power consumption is lower than 50mW. Finally, the large neighborhood universal machine is proposed. By using the large neighborhood cellular neural network as the core-computing unit, the analog array processor is realized. Some local memories are added into the single LN-CNN cell. There are also local communication and control unit inside the cell. Many complicated tasks that cannot be compute at one time by LN-CNN can be solve by the universal machine. From the above results, the proposed LN-CNN has great potential in the implementation of the CNN universal machine for various signal-processing applications. Further researches in this field will be conducted in the future. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT890428033 http://hdl.handle.net/11536/67105 |
顯示於類別: | 畢業論文 |