Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 何健豪 | en_US |
dc.contributor.author | Jian-Hau Her | en_US |
dc.contributor.author | 林大衛 | en_US |
dc.contributor.author | Dr. David W. Lin | en_US |
dc.date.accessioned | 2014-12-12T02:25:26Z | - |
dc.date.available | 2014-12-12T02:25:26Z | - |
dc.date.issued | 2000 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT890428034 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/67106 | - |
dc.description.abstract | 隨著對多重使用者偵測的理論基礎以及處理數位訊號,混合訊號,和RF訊號的技術發展,使得根據多重使用者偵測理論的直接序列/分碼多工接收器變得可行。由於減法干擾消除器的複雜度較低,因此實際實現多重使用者偵測時多是使用此種架構。在這篇論文裡,我們根據平行干擾消除器實現一個3GPP的直接序列/分碼多工接收器以及一個對應的通道模擬器。我們使用桌上型電腦作為主控中心,一塊DSP板用以實現無線通道模擬器以及平行干擾消除接收器。在無線通道模擬器中我們模擬多重路徑Rayleigh淡化對基頻傳輸訊號的影響。在平行干擾消除接收器的實現中,我們使用一些方式來降低系統複雜度。另外我們在主控中心裡使用多工同步系統以增加效能和降低設計的複雜度。目前在5個使用者,每個使用者只有一條路徑,且只有一根天線的情形下,通道模擬器和平行干擾消除接收器的處理速度可以達到每秒4.1百萬筆資料 (chip). | zh_TW |
dc.description.abstract | The improved understanding of the theoretical basis of multiuser detection and advances in digital,mixed-signal,and RF technologies let the realization of advanced DS-CDMA receive based on multiuser detection principles become a eality.Due to the lowe complexity, subtractive interference cancellation approaches are attractive for practical implementation of multiuser detection.In this thesis,we implement a 3GPP DS-CDMA receive based on parallel interference cancellation (PIC)together with a corresponding wireless channel simulator.A desktop PC acts as the controller,and a DSP-embedded card is employed to implement the wireless channel simulato and the PIC eceiver.In wireless channel simulation,we simulate the e ffect of multipath Rayleigh fading on the transmitted signal at baseband.The implementation of the PIC eceive employs some techniques to reduce the complexity.For e fficiency and ease of programming,multithreading is adopted in the controller.When there are 5 users,a single path for each user,and a single antenna in the system,the processing speed of the channel simulator is 4.1M chips per second and that of the PIC receive at the initial stage is also 4.1M chips per second. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | 訊號處理器 | zh_TW |
dc.subject | 平行干擾消除技術 | zh_TW |
dc.subject | DSP | en_US |
dc.subject | PIC | en_US |
dc.title | 使用平行干擾消除技術之CDMA接收器在數訊號處理器上之實現 | zh_TW |
dc.title | DSP Implementation of CDMA Receiver Base on Parallel Interference Cancellation | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
Appears in Collections: | Thesis |