針對應用硬體規格描述語言之電路設計的功能性錯誤診斷

Abstract

在現今設計的流程中，實現的設計以及設計規格之間在功能上的不吻合經常會發生。然而，因為現今的數位設計的複雜度越來越高的情況之下，以人力從程式中找到錯誤的位置越顯困難。在這篇論文裡，我們針對自動功能性錯誤診斷提出了一個有效的方法。一個可以處理多個設計錯誤且僅需一個能導致錯誤之測試向量的方法。對於錯誤可能發生的範圍，我們首先先去除掉一堆不可能為錯誤的敘述以獲得一個敘述的集合稱之為錯誤空間(error space)。再者，我們試著評估在錯誤空間裡的敘述為正確敘述的可能性。根據這些評估出來的可能性，我們以一個優先次序將這些敘述顯示出來。因為這樣的顯示的關係，使用者非常有可能地在前幾次搜尋下就發現錯誤的來源，如此一來花在尋找錯誤上的功夫就可以大幅縮短。由我們所做的幾個實驗中，我們可以錯誤空間的大小確實是小的，而且真正導致錯誤的敘述也總是被顯示在前面幾行。證實我們的方式確實是有效的。

Functional mismatches between the register-transfer-level (RTL) HDL simulation and the specification often occur during the design stage. However, the complexity of modern designs is getting higher and higher such that manually tracing the codes to find the bugs becomes more and more difficult. In this thesis, we propose an effective approach for automatic functional error diagnosis, which can handle multiple errors with only one erroneous test case. For the error candidates, we will first eliminate some impossible statements to obtain a smaller set of statements, which is called the error space. Then, we will try to estimate the possibility of being correct for each statement in the error space with some heuristics and display those statements in a prioritized order according to their possibility. It can be very helpful because users are very possible to find their bugs in the first few terms such that the debugging efforts to trace all error candidates can be significantly reduced. Conducting some experiments on several designs, we can show that the size of the error space is indeed small and the true erroneous statements are always displayed in the first few lines with the proposed techniques.