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dc.contributor.author郭顯豐en_US
dc.contributor.authorHsien-Feng Kuoen_US
dc.contributor.author陳紹基 en_US
dc.contributor.authorDr. Sau-Gee Chenen_US
dc.date.accessioned2014-12-12T02:25:30Z-
dc.date.available2014-12-12T02:25:30Z-
dc.date.issued2000en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT890428058en_US
dc.identifier.urihttp://hdl.handle.net/11536/67132-
dc.description.abstract本論文提出第三代行動通訊(寬頻分碼多工存取)系統中耙狀接收機之數位訊號處理器的實現與低功率的設計,包含傳統耙狀接收機、適應性最小均方差耙狀接收機、線性內插通道估測與滑動窗型通道估測之定點及浮點、執行效能、錯誤率與運算複雜度的比較。另外由於低功率設計對於可攜式應用是愈來愈重要的,我們亦提出了一些低功率相關器的設計,並比較了不同速度與電壓之下各種相關器的功率消耗。zh_TW
dc.description.abstractIn this thesis, the DSP realization and low-power design of the Rake receiver in the third Generation Mobil Communication (Wideband Code Division Multiple Access) systems were presented. The conventional Rake receiver and adaptive LMMSE Rake receiver with channel estimation of linear interpolation and sliding window were realized, with fixed-point and floating-point operations. Their performances are compared, including BER and computational complexities. Since low-power design is critical for portable applications, some new low-power correlators were proposed. We compared the power consumption of different correlators in different speeds and voltages.en_US
dc.language.isozh_TWen_US
dc.subject耙狀接收機zh_TW
dc.subject數位訊號處理器zh_TW
dc.subject通道估測zh_TW
dc.subject低功率設計zh_TW
dc.subject相關器zh_TW
dc.subjectRake receiveren_US
dc.subjectDSPen_US
dc.subjectchannel estimationen_US
dc.subjectlow-power designen_US
dc.subjectcorrelatoren_US
dc.subjectWCDMAen_US
dc.subjectLMMSEen_US
dc.title第三代耙狀接收機之低功率設計與DSP實現zh_TW
dc.titleLow-power Design of 3G Rake Receiver & Its DSP Realizationen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文