內插器硬體電路設計

Abstract

隨著科技的進步，無論是積體電路的製程，還是微機電元件的設計，都由微米朝向次微米邁進。又由於一般的測距定位感測器解析度，是有其上限，例如一般常用之測距定位光學尺，其光柵狹縫寬為20um。所以應用在製程設備上如光罩機和步進機等，有解析度不足的問題。如果要更進一步製做光柵狹縫寬度小於20um的光學尺，不論是用蝕刻或是印刷方式，其所需要付出的製做成本是相當的高。所以採用電路的設計，將測距定位感測器所輸出的似弦波訊號，作等分內插處理，可以得到40等距分割的效果，可將解析度提高40倍，對半導體製程所需要的解析度，有相當大的助益。另外在一般機械臂行程定位控制中，也可以利用此內插器晶片，降低測距定位用感測器的成本。 內插器晶片設計上，是採用比較器法，由UMC 0.5um Double-poly Double-metal COMS製程製作，核心線路為1000´600 mm2，前級訊號處理線路為850´760 mm2，可達40倍分割之解析度，工作頻率可達50Hz，秏電量為50mW。此結果可應用於各式量測系統中，增加其解析度，或是用來降低量測系統設備硬體的成本。

The laser graphic generator and stepper are important in Micro-Electro-Mechanical System (MEMS) and semiconductor. Inside these generators and steppers, opitcal incremental encoders are wildly used to measure angles or distances. The resolution of opitcal incremental encoder is limited by manufacture process. The higher the resolution, the more it costs. Interpolating encoder output sine/cosine signals can upgrade the resolution forty times and achieves to 0.5 micrometer. The analog/digital flash structure was chosen because of its faster and not too complex. The chip can be seen as a product, since its good cost/piece. The chip is fabricated in a UMC 0.5um CMOS Double-poly Doubly-metal process. The main core layout area is 1000´600 . The current to voltage converter core layout is 850´760 . Peak to peak input sine/cosine voltages in the range of 0v to 5v are processed with a 50kHz signal bandwidth and an interpolation factor of 5to 10. Average power consumption is 50mW. The result can be contribution to the whole measuring system or to lower the requirements to the scale.