應用於無線多媒體傳輸以餘弦函數轉換為基礎且抗錯誤的位元層壓縮編解碼器之設計

Abstract

隨著數位媒體的需求增加，有非常多的研究投入於影像或動態影片傳輸服務的發展。因為傳輸通道有頻寬的限制，壓縮的技巧就被用於降低傳送的資料量。雖然壓縮率達到了，但資料之間形成很強的關聯性。當通道因為雜訊和干擾等等問題而惡化時，影像的畫質就會突然間降低。所以目前有非常多的努力用於在壓縮的資料流(bit-stream)上建立抗雜訊的能力，還有確保在有雜訊的環境下仍能改進傳送影像或動態影片的畫質。 我們提出了位元層的抗雜訊壓縮(Bit-Plane EREC)。在相同的畫質下(PSNR)，壓縮的資料量平均低於JPEG 5%。我們也在不同的BER下做模擬，發現既使在BER為0.1%下，畫質(PSNR)仍有26dB。此外，我們也和EREC[24]作比較，發現畫質表現高於EREC [24]，但是我們演算法的複雜度卻低於它許多。 我們的Bit-Plane EREC可以在工作時脈20MHz下，壓縮/解壓縮CIF size (352 x 288)(format：4:2:0)的影像每秒30張。在TSMC 0.35mm 1P4M CMOS製程技術下及使用Avanti 0.35mm的標準元作庫，此架構使用約43K個邏輯閘(gates)，晶片核心面積為2.95´2.95mm2。Post-layout測試結果顯示本架構之晶片時脈速度最高可達125MHz在供電3.3V下。另外，在時脈100MHz下，壓縮和解壓縮的耗電量分別為0.255W 和0.222W。

With the increasing demand for digital media, there has been significant interest in the deployment of image and video communication services. As communication channels are limited in bandwidth, compression techniques are employed to reduce the amount of information to be transmitted. While the bit rate reduction is achieved, a strong data dependency is created. When the channel deteriorates because of noise, interference, and so on, the picture quality can suffer abruptly. Much effort has been invested in R&D to build error resilience into the compressed bit-stream and ensure improving the quality of image/video transmission in noisy or error-prone environment. We propose our proposed Bit-Plane EREC. The average compressed rate is 5% less than JPEG standard with the same image quality (PSNR). We also simulated our algorithm at different BERs, and we find that even at high BER of 0.1%, it can still achieve high image quality (PSNR = 26dB). Besides, we compare our algorithm with EREC [24]. We find that our performance higher than EREC [24], however our algorithm complexity is lower than it. Our Bit-Plane EREC image codec can compress and decompress CIF size (352 x 288)(format：4:2:0) images at the rate of 30 frames per second at clock rate 20MHz. The EREC image codec has been fabricated in TSMC 0.35μm 1P4M CMOS technology. The chip integrates 43k gates and occupies a silicon area of 2.95 x 2.95 mm2. The post-layout simulation shows that our chip can operate with clock rate up to 125 MHz at 3.3V power supply. Besides, at clock rate 100MHz the power consumption is 0.255W and 0.222W for encoding and decoding, respectively.