標題: | 探討矽在絕緣層上元件之扭結效應的形成及利用扭結效應來製作單電晶體動態存取記憶體之可行性 Study on the Formation of Kink Effect in SOI Device and the Feasibility of Using Kink Effect to Build a Single-Transistor DRAM |
作者: | 楊皓然 Hau-Ran Yang 吳慶源 Ching-Yuan Wu 電子研究所 |
關鍵字: | 扭結效應;矽在絕緣層上;單電晶體動態隨機存取記憶體;碰撞游離化;多餘電洞;Kink Effect;Silicon on Insulator (SOI);Single-Transistor DRAM;Impact Ionization;Excess Holes |
公開日期: | 2000 |
摘要: | 在本篇論文中,我們將探討在矽在絕緣層上 (SOI) 中利用扭結效應(Kink effect) 改變臨界電壓 (Threshold Voltage) 的特性來製作一個單電晶體動態隨機存取記憶體的可行性,以及嘗試利用Medici模擬軟體來驗證扭結效應形成的真正原因是否如一般彷間書籍所敘述:”由游離碰撞所產生的多餘電洞將會累積並導致扭結效應 ”。
第一章為對本篇論文之簡介。第二章將說明一般論文及書籍上描述扭結效應形成的原因。在一般書籍上描述扭結效應形成的主要原因為多餘的自由電洞 (Free holes) 不能即時地排出,因而累積 (Accumulate) 在SOI底部,而由於電洞的累積使電位升高,導致產生體效應 (Body effect) 使臨界電壓降低,進而產生扭結效應。
但是扭結效應形成原因真的只有如一般所描述的嗎?如果真的是如此,在一般書籍中似乎並沒有合理地探討是否合乎電中性原理。在第三章中,我們認為電洞將累積到一順向偏壓的電壓,這個電壓是由埋入氧化層電容 (Buried Oxide Capacitance) 對地所提供的。這個順向電壓將使”體源接面” (Body-Source Junction)產生足夠的順偏電流排掉緊接而來的多餘電洞。隨著電流和電洞累積達到平衡,接面電壓 (Junction Voltage) 將形成扭結效應的重要部份。除此之外我們推測形成扭結效應的還有另一部份,是由自由電洞的流動形成的電壓降所構成的。但是經由我們所推導的解析模型模擬的結果我可以發現電壓降的部份遠小於接面部份的電壓。利用Avant! Medici模擬軟體來進行模擬,經由改變基底角落的參雜濃度來改變基底的相對電阻值,我們可以發現扭結效應並沒有因此而產生巨大的影響。因此,可以確定扭結效應是由接面電壓所主導的。另外值得注意的是,累積在矽在絕緣層上 (SOI) 底部的電洞只是所有碰撞游離化電洞中的極小部份,其中之一的證據是埋入氧化層電容實在太小了,所以電洞累積量也相當少。所以扭結效應是由累積電洞所造成的說法並不是很正確。它實際形成的原因應該是由於多餘電洞流動所形成的類費米 (Quasi-Fermi) 電位所形成的。我們經由這個論點嘗試地推導出真實模擬扭結效應的模型,此模型將在第三章作詳盡的描述和推導。
在上述的論點基礎下,我們將探討利用扭結效應製作一種單電晶體的動態隨機存取記憶體的可行性。第四章中,我們將利用扭結效應改變臨界電壓的原理,外加製造一個較大的電位能障 (Potential Barrier) 和較大的埋入氧化層電容(Buried Oxide Capacitance) 使較多電洞滯留,進而增大在臨界電壓的改變來運作動態隨機存取記憶體的邏輯特性,因此我們不需要外加額外的電容。因此,一個高速及高密度的動態存取記憶體便可以得到。在第五章中,我們討論本篇論文的貢獻以及未來改進的方向與更深入研究的主題。 In this thesis, we would investigate into the feasibility about using the characteristic, which Kink effect changes threshold voltage, to build a One-Transistor-DRAM and use a numerical simulator ”Medici” to determine “the holes produced by Impact Ionization would accumulate and induce Kink effect. ” or not. Chapter 1 gives the introduction of this thesis. In Chapter 2, we will illustrate the formation of Kink effect, which most people think. Generally speaking, the major reason of forming Kink effect is excess free holes can’t drain away immediately and accumulate at the bottom of SOI structure to rise body potential and induce body effect. Then, it would cause threshold voltage variation and then bring Kink effect. But is it true that the composition of Kink effect is as people said in general? If it is, the statement in general publications seems not match the principle of Electrical-Neutrality. In Chapter 3, we considered that excess holes would accumulate until reaching a forward bias voltage, which is provided by the buried oxide capacitor to ground. The voltage can forward bias the body-source junction and induce a proper current, which is equal to excess-holes flowing. As reaching equilibrium, the junction voltage would play a significant part on inducing Kink effect. The other part we assume to form Kink effect is the voltage drop of current flowing. But in our analytical-model results we can see the order is much less than junction voltage. Utilizing a numerical simulator “Medici” of Avant!, we found that the Kink effect doesn’t have huge influence when we modified the doping concentration at the bottom of SOI. So we can sure that Kink effect is dominated by junction voltage. Besides, it is worthy to know that the part of excess holes accumulated at bottom is extremely smaller than all excess holes induced by impact ionization, and is the cause of the extremely small value of buried oxide capacitor. Hence, the statement that Kink effect induced by accumulated holes seems not well. It is induced by the Quasi-Fermi potential, which is formed by excess holes flowing. Then, we try to derive the simulation model of Kink effect by our point of view. In Chapter 3 we will describe and derive the Kink effect model precisely. Based on the points of view as discussed before, we will discuss the feasibility about using Kink effect to build a One-Transistor DRAM. In Chapter 4, we will utilize this characteristic that Kink effect would modify threshold voltage, and build a larger potential barrier and buried oxide capacitor to trap more excess holes, to function the logic of DRAM. Hence, we don’t need a capacitor for this DRAM externally, that’s why we call it a “Single Transistor DRAM”. Finally, in Chapter 5, the major contribution of this thesis and future researches are summarized. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT890428121 http://hdl.handle.net/11536/67198 |
顯示於類別: | 畢業論文 |