具有電場感應汲極之薄膜電晶體的研製與分析

Abstract

本篇論文中，我們首先提出，且成功製造兩種新型底座閘極薄膜電晶體元件，分別具有自我對準與非自我對準之製程特性。此兩種底座閘極薄膜電晶體於電性上的操作，均具有電場感應汲極的優點及特性。 首先，我們以傳統薄膜電晶體之電性，來與此兩種新結構的實驗結果比較。於非自我對準之底座閘極元件中，我們發現此結構不但能成功的抑制閘極引致汲極漏電流效應，並且還可以保持極高的驅動電流能力。以W/L=10μm/4μm的元件為例，對非自我對準之N型通道薄膜電晶體而言，當汲極電壓為15.1 V，且閘極電壓由-5 V漸漸升高到20 V時，最小的關閉電流為25.8 pA，最大的導通電流為97.3 μA，所以導通與關閉電流的比率為3.8’106; 相同的，對非自我對準之P型通道薄膜電晶體而言，當汲極電壓為-15.1 V，且閘極電壓由5 V漸漸下降到-20 V時，最小的關閉電流為18.8 pA，最大的導通電流為66.4 μA，所以導通與關閉電流的比率為3.5’106。值得一提的是，此結構之製程若應用於透明之玻璃基板時，可藉由從玻璃基板端曝光，並以底座閘極作為遮幕，亦可成為自我對準之製程。 對自我對準之底座閘極元件而言，除了對閘極引致汲極漏電流效應的抑制效果外，我們可以得到相似於非自我對準之底座閘極元件的電性結果。雖然不像自我對準元件般能完全抑制閘極引致汲極漏電流效應，但是此結構仍然可以大量的減少閘極引致汲極漏電流的效應，近而得到較低的關閉電流。由此可知於底座閘極結構之薄膜電晶體中，我們可以得到非常好的電性特性。除此之外，此結構亦可抑制短通道效應，即使當通道長度縮短到1.5μm時，我們仍可得到不錯的操作特性。 於此新型結構中，底座閘極於元件操作時扮演一個重要的角色，因為當底座閘極電壓越大時，所得到之導通與關閉電流的比率亦是最大的，所我們於N和P型通道薄膜電晶體操作時，底座閘極電壓分別加壓在±40 V。 同時我們亦討論不同的氫化處理方式對於元件的影響，結果發現用NH3電漿處理會比H2電漿處理有較好的元件特性，這是因為H2的離子撞擊截面比NH3小，所以導致H2電漿處理不能有效的產生氫離子或原子去填補通道中的缺陷陷阱。此外，NH3電漿處理時會有許多的氮堆積在SiO2與poly-Si的界面上，可藉此填補通道中的缺陷，進而形成強韌的Si-N鍵結。 此外，電場感應汲極接面會呈現一種阻止漏電流的現象，由此我們可以解釋為何此結構會比傳統結構擁有還要低的漏電流。並且藉由對漏電電流的仔細分析，我們可以運用熱載子放射機制(thermionic emission)、與缺陷(defect)有關的載子穿透機制(thermal field emission)、及汲極引致能障降低(drain-induced barrier lowering)效應，來幫助我們解釋此結構的漏電電流的機制。

In this thesis, TFT devices with either a self-aligned or non-self-aligned bottom sub-gate structure were proposed and successfully fabricated. The two sub-gate configurations allow the formation of FID (field-induced-drain) structure in the device operation. First, the experimental results were compared with those of conventional TFTs. In non-self-aligned bottom sub-gate devices with FID structure (bottom-sub-gate FID TFTs), they not only successfully reduce the GIDL (gate-induced-drain leakage)-like anomalous leakage current, but also maintain a high drive current capability. Specifically, 25.8 pA and 18.8 pA in off-state currents, 97.3 μA and 66.4 μA in on-state currents, and 3.8’106 and 3.5’106 in the on/off current ratios are successfully obtained for n- and p-channel bottom-sub-gate FID TFTs with W/L=10μm/4μm, respectively. The above results are obtained at VD=15.1 V, with VG ranging from -5 V to 20 V for n-channel TFTs, and VD=-15.1 V, with VG ranging from 5 V to -20 V for p-channel TFTs. It is worth noting that the proposed structure can actually result in a self-aligned structure, if applied to transparent glass substrate. This can be achieved by substrate-side exposure, and by using the bottom subgate to serve as the photo mask. As for the self-aligned bottom sub-gate devices with FID structure (bottom-sub-gate SAFID TFTs), they depict good electrical performance similar to that of bottom-sub-gate FID TFTs, except for the slightly larger GIDL-like leakage current. Nonetheless, it can still significantly reduce the GIDL-like leakage current, compared to the conventional counterparts. Therefore superior performance is realized with the proposed bottom sub-gate scheme. Moreover, the short channel effect is also effectively suppressed in the new structures with subgate. Well-behaved performance is observed even if the channel length is down to 1.5 μm. The sub-gate effect is also investigated. When the sub-gate bias changes from 0 V to ±40 V, the on/off current ratios increase from 3.5’102 to 4’105, and from 17 to 3’106 for n- and p-channel TFT, respectively. It appears therefore that the optimum voltages of the subgate are ±40 V for both n- and p-channel TFT, respectively. The effects of NH3- and H2-plasma treatment on both n- and p-channel bottom-sub-gate TFTs were investigated. It was found that the NH3-plasma treatment is more effective in passivating the trap states of the device than H2-plasma treatment. Hence, it is more effective in improving the electrical performance of the device, such as subthreshold swing, threshold voltage, leakage current, on-state current, and on/off current ratio. Both nitrogen pile-up at the SiO2/poly-Si interface and the strong Si-N bond formation to passivate the dangling bonds at the grain boundaries in the channel region are believed to be responsible for the observed improvement. Because the anomalous leakage current inherent in poly-Si TFTs can be effectively blocked at the FID junction, this explains why TFTs with FID structure have a lower off-state current, compared to the conventional TFTs. To further elucidate this effect, Off-state leakage mechanisms of the device were also investigated by measuring the activation energy. Thermionic emission of electrons and trap-assisted field emission processes are considered to explain the results. When channel length is scaled down, drain-induced barrier lowering (DIBL) effect would occur, and could explain the significant leakage current increase in the bottom-sub-gate SAFID TFTs.