超寬頻無線網路應用之互補金氧半高動態範圍可變增益放大器設計

Abstract

本論文針對超寬頻(UWB)無線網路應用提出低功率高動態範圍可變增益放大器之設計。本文提出之可變增益放大器 (VGA)採用高範圍的假指數電路架構，此架構分別提供單級約30dB之可變動態範圍，在高動態範圍的架構下，以較少的串接級來達到所需的動態範圍並以達成低功耗和寬頻之設計目標。將此可變增益放大器架構應用於超寬頻射頻前端接收器，加上後級放大器，以符合高增益之要求，並且增加一組回授二階濾波器，以補償電路不匹配之直流電壓偏移，進而有助於提升整體可變增益放大器之效能。經由0.18-μm CMOS 製程進行電路實作，量測出230MHz的大頻寬與約9.5~11.2mW的低功耗，同時具有73dB的最大功率增益、21.5dB的最低增益值，並在400mVpp輸出電壓時得40dB全諧波失真，驗證此高動態範圍之可變增益放大器電路架構之優點。此超寬頻射頻前端接收器參考多頻帶正交頻率多重分割技術規格草案的需求。

This thesis presents a low-power design of a CMOS high dynamic variable gain amplifier (VGA) for ultra-wideband (UWB) wireless applications. To achieve low power consumption and wide operating bandwidth, the proposed VGA employing a wide-range pseudo-exponential circuit topology is presented, which can provide about 30dB dynamic per-stage. With the proposed topology, the amplifier stages capable of achieving a required gain range can be reduced and the level of power consumption is tremendously lowered. The novel topology of low power UWB VGA is applied to the RF front-end design for the UWB direct conversion receiver. A wideband post amplifier is designed for the purpose of high gain. The DC offset voltage will be reduced by a feedback 2nd order low-pass filter and consequently help improving overall performance of the VGA. A circuit implementation in 0.18-μm CMOS process shows a 230MHz bandwidth. The amplifier provides a maximum forward gain of 73 dB while drawing 11.2 mW and a minimum forward gain of 21.5 dB while drawing 9.4 mW from a 1.8-V supply. The harmonic distortion is batter than 40dB under the output signal magnitude is 400m Vpp. In this thesis, design optimization for the variable gain amplifiers in wide bandwidth applications is also verified. The UWB receiver front-end referenced to the Multi-Band OFDM with operation frequency range 3-10 GHz demonstrates low power, high gain, and wide bandwidth.