完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 謝百舉 | en_US |
dc.contributor.author | Bai-Jue Shieh | en_US |
dc.contributor.author | 李鎮宜 | en_US |
dc.contributor.author | Chen-Yi Lee | en_US |
dc.date.accessioned | 2014-12-12T02:25:38Z | - |
dc.date.available | 2014-12-12T02:25:38Z | - |
dc.date.issued | 2000 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT890428146 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/67227 | - |
dc.description.abstract | 在此論文中,我們提出以記憶體為基礎之可變長度編解碼器的演算法和硬體架構設計,有系統的最佳化流程使得記憶體需求減少以及操作輸出率增加,對於實際的多媒體和通訊應用而言,實現了完全可程式的高效率壓縮與解壓縮方案。 此論文首先提出預測單一位元資料流內編碼字元邊界的演算法,打斷可變長度解碼時,所產生的遞廻依序關係。由於編碼字元長度可以在解碼流程完成之前就預先知道,因此多處理器的硬體架構可以用來處理單一位元資料流,而大幅增加解碼輸出率,有了這項改進,此可變長度解碼器就能夠被大部分的應用所採納。 為了簡化資料輸出入的控制和進一步增加效能,我們提出以群組為基礎之可變長度編解碼器設計,並且達到編碼表完全可程式化。因為記憶體需求被編碼字元群組化和符號轉換法有效地減少,所以編碼表和符號都可以存入記憶體中,採用平行的群組搜尋法,可變長度編解碼器得到固定速率的壓縮和解壓縮,即一個時脈週期一個符號;此外,由於群組的資料是共用的,可以同時編碼和解碼的操作流程得以實現;所以,此可變長度編解碼器的設計滿足了高效能系統和互動式通訊的需求。 根據以群組為基礎之可變長度編解碼演算法,我們發展出一個全新的多編碼表融合法,以在有限的記憶體空間內,達到多編碼表可程式。使用編碼表融合法,編碼表間的多餘訊息會被抽離,而達到記憶體的整體最佳化,因此所有的編碼表資料是以可容許的記憶體空間來儲存,這使得編碼表的切換是經由選擇不同的記憶體內容來達成,而非重新輸入編碼表資料;因為記憶體空間和編碼表切換時間都獲得有意義地減少,對於實際的應用而言,即使使用中的編碼表常常在更替,所實現的可變長度編解碼器仍然達到高效能與低成本的要求。 然後,我們提出一個採用多編碼表融合之可變長度編解碼器的影像解碼器架構。因為使用以記憶體為基礎之可變長度解碼器,此影像解碼器擁有可改造和可程式的特性,而適用於多種編碼方案,由於有效的管線化設計,可變長度解碼器仍然維持其操作速率,並且每一個時脈週期都可以處理一個編碼字元;此影像解碼器使用0.35-mm CMOS的製程技術加以實現,模擬的結果顯示,在 66MHz 的時脈頻率下,所提出的可變長度解碼器,其輸出率為 56.5M symbols/sec,而影像解碼器的解壓縮率更可以達到400M pixels/sec;由此可知,所提出的以記憶體為基礎之可變長度編解碼器非常適合實際的應用系統。 最後,我們描述影像解碼器所使用的設計方法,以減少功能方塊和系統整合的設計複雜度。此外,我們討論了以記憶體為基礎之可變長度編解碼器的設計指引,使所提出的設計能夠被重複使用在各種不同的應用和系統架構中。 | zh_TW |
dc.description.abstract | In this dissertation, the algorithm and architecture of memory-based VLC codec designs are presented. Systematic optimization procedures are proposed to reduce the memory requirements and increase the operation throughputs. Efficient compression and decompression schemes with full programmability are achieved for real applications in multimedia and communications. This dissertation first presents an algorithm to predict the codeword-boundary in a single bitstream for breaking the recursive dependence of VLC decompression. Codelengths are known before decoding procedures are completed. Hence, a multi-processor architecture is used to deal with a single codeword bitstream and increase the decoding throughput. With this improvement, the VLC decoder can be utilized by most applications. In order to simplify IO conditions and further enhance performance, a group-based VLC codec design with full table programmability is proposed. Both coding tables and symbols are loaded into memories because memory requirements are reduced significantly by a codeword grouping and symbol conversion. With parallel group searching, the VLC codec obtains a constant symbol rate, i.e. one symbol per clock cycle. Owing to that the group information is shared, concurrent encoding and decoding procedures are carried out. Consequently, this VLC codec design satisfies the requirements of high performance systems and interactive communications. According to the group-based VLC codec scheme, a novel multi-table merging approach is developed to achieve multi-table programmability with a limited memory space. By the table merging methods, information redundancies among coding tables are explored and global memory requirement optimization is fulfilled. Then, the data of all used tables are stored in memories. Table changing is preformed by switching rather than reloading the memory contents. Since both memory space and table switching time are saved, an area efficient and high throughput memory-based VLC codec design is realized for practical applications, where the used table is changed frequently. Employing the multi-table-merged VLC codec, a video decoder architecture is presented. Due to the memory-based VLD, the video decoder acquires the adaptability and programmability for various coding schemes. Because of efficient pipelining, the VLD module maintains the operation rate and processes one codeword per clock cycle. This video decoder is implemented in 0.35-mm CMOS technology. Simulation results show that the throughput of the proposed VLC decoder is up to 56.5M symbols/sec and the decompression rate of the video decoder is 400M pixels/sec with a clock rate of 66MHz. As a result, the proposed memory-based VLC codec is quite suitable for real application systems. Finally, the design methodology used by the video decoder is described for reducing the complexity of function unit design and system integration. Additionally, the design guidelines of the memory-based VLC codec are discussed for reusing it in versatile applications and different system architectures. | en_US |
dc.language.iso | zh_TW | en_US |
dc.subject | 可變長度編碼 | zh_TW |
dc.subject | 霍夫曼編碼 | zh_TW |
dc.subject | 動態影像專家群 | zh_TW |
dc.subject | 動態影像解碼器 | zh_TW |
dc.subject | 高畫質數位影像電視 | zh_TW |
dc.subject | VLC | en_US |
dc.subject | Huffman code | en_US |
dc.subject | MPEG | en_US |
dc.subject | video decoder | en_US |
dc.subject | HDTV | en_US |
dc.title | 以記憶體為基礎之高效能可變長度編解碼器設計 | zh_TW |
dc.title | Area Efficient and High Throughput Memory-Based VLC Codec Designs | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |