數位接收機上降率訊號的記號時脈同步

Abstract

在本論文裡，我們將模擬一個數位傳送機與接收機的整體運作過程。數位通訊系統中，因為採用載波調變的緣故，訊號的取樣速率必須隨之轉換。傳送端將經過升率再調變的訊號發送出來，而在接收端進行相對應的載波解調，之後進行降率的動作。在降率的同時也產生了不同相位的取樣組點的選擇。本論文所要討論的主題即是如何選取降率後最適當的相位組點。我們將介紹採用記號同步器與時脈錯誤偵測器兩種架構合併的方法，藉以獲得在數位接收機中降率訊號的最佳相位組點，使得後級的抉擇元件能達到更正確的記號評判，減少位元錯誤率。最後也將討論另一種不使用時脈錯誤偵測器的接收機架構，並比較其與第一種架構的使用條件與優劣。

In this thesis, we will simulate the full process procedure of a digital transmitter and receiver. In a digital communication system, since we modulated the signal with a higher frequency carrier, the sampling rate of signal should be changed. At the transmitter, we transmitted the interpolated and modulated signal into the channel, and at the receiver, we perform the corresponded carrier demodulation, and then decimate the signal. When we decimated the signal, it will cause the selection problem of different phase samples sets. The main issue of this thesis is how to choose the proper samples set after decimation. We will introduce a method which combine symbol synchronizer and timing error detector to solve our problem. We will show that this method could catch the best samples set and the decision device could make more correct symbol decision. In the end, we will also introduce another receiver structure without timing error detector, and compare it with the first one.