分碼多重進接系統的接收機架構設計之研究

Abstract

分碼多重進接(Code-Division Multiple Access,CDMA)被認為是有希望應用在未來無線通訊的一種技術。在本論文當中，我們提出一種分碼多重進接系統的接收機架構。這個接收機架構包括一個將射頻訊號轉換到數位基頻訊號的低中頻架構以及一個用來解調CDMA訊號的數位犁耙式接收機。 我們將藉由電腦模擬的方式來評估此低中頻架構及數位犁耙式接收機兩者的效能。 在低中頻架構方面，我們提出一個混合式影像消除的方法。這種混合式影像消除的方法包含了一個改良式哈特利(Hartley)影像消除混波器及一個基頻數位式影像消除處理器。 這個改良式哈特利影像消除混波器和原來哈特利影像消除接收機具有相似的效能，而所不同的是，這個改良式哈特利影像消除混波器提供了兩個數位輸出。其中一個數位輸出加強了欲取訊號的強度， 而另外一個數位輸出則加強了影像訊號的強度。數位式影像消除處理器首先量測類比元件當中的不匹配效應(mismatching effect)，然後再藉由補償這個不匹配效應來消除影像訊號。並且，我們也針對這種混合式影像消除接收機提出了一個簡化的製作方式，以降低該接收機的計算複雜度。在考慮由類比/數位轉換器所產生的量化效應(quantization effect)之下， 我們利用電腦的模擬來評估這個簡化製作方式的效能。根據電腦模擬的結果顯示，所提出的這種混合式影像消除接收機的影像訊號消除比例遠大於原來哈特利影像消除接收機的影像訊號消除比例。而採用這種架構可以大大地降低類比元件當中對於匹配(matching)的規格要求。 在數位犁耙式接收機方面，我們提出了一個具有新的多重路徑搜尋機制的犁耙式接收機。在這個新的多重路徑搜尋機制當中，我們利用一個快速搜尋器及一個啟發式路徑選擇器，來估測針對於多重路徑衰減頻道當中預定數目個展頻碼相位移。除此之外，我們利用一個藉由前饋式頻道量測技術的量測子系統，來追蹤快速變化的頻道脈衝響應。這個快速搜尋器粗略地估測出展頻碼相位移。並且，這個以一種啟發式路徑選擇演算法來運作的啟發式路徑選擇器，將根據快速搜尋器的輸出結果及量測子系統的輸出結果，來決定出一組更可靠的展頻碼相位移。在犁耙式接收機方面，我們採用了領航訊號消除技術來增進系統的性能。我們利用電腦的模擬來評估這個新的多重路徑搜尋機制的暫態響應以及整個犁耙式接收機的平均誤碼率(Bit Error Rate,BER)。電腦模擬的結果顯示，這個數位犁耙式接收機在無線行動頻道當中運作良好。 整體而言，這個針對分碼多重進接系統所提出的接收機架構不但具有很好的效能，並且複雜度低，很適合作為積體電路的製作。

Code division multiple access (CDMA) is considered to be a promising technology for future wireless communications. In this dissertation, we proposed a receiver architecture for CDMA systems. The receiver architecture includes a low-IF architecture which translates the RF signal to the digital baseband signal, and a digital RAKE receiver which demodulates the CDMA signal. The performances of both the low-IF architecture and the digital RAKE receiver are evaluated by computer simulations. In the low-IF architecture, we proposed a hybrid image rejection method. The hybrid image rejection method includes a modified Hartley image rejection mixer and a baseband digital image rejection processor. The modified image rejection mixer has similar performance as the original Hartley image rejection receiver but provides two digital outputs. In one output it enhances the desired signal and in the other output it enhances the image signal. The digital image rejection processor first measures the mismatching effect in the analog devices and then suppresses the image signal by compensating for the mismatching effect. We also propose a simplified implementation method for the hybrid image rejection receiver to reduce its computation complexity. Computer simulation was used to evaluate the performance of this simplified implementation method including the quantization effect of the A/D converters. Simulation results show that the proposed hybrid image rejection receiver achieves much better image rejection ratio than the original Hartley image rejection receiver. The adoption of this architecture greatly relaxes the matching requirements in the analog devices. In the digital RAKE receiver, we proposed a RAKE receiver with a new multipath search scheme. In this new multipath search scheme, we employ a fast searcher and a heuristic path selector to estimate a predetermined number of the code phase delays for the multipath fading channel. Besides, a sounding subsystem which utilizes a feedforward channel sounding technique is used to track the rapidly changing impulse response. The fast searcher detects the code phase delays coarsely and the heuristic path selector which is operated on a heuristic path selection algorithm decides a more reliable set of the code phase delays according to both the outputs of the fast searcher and the sounding subsystem. In the RAKE receiver, we adopt a pilot interference cancellation technique to improve the system performance. Both the transient performance of the new multipath search scheme and the average BER performance of the RAKE receiver were evaluated by computer simulations. The simulation results show that the proposed RAKE receiver performs well in a radio mobile channel. In overall, the proposed receiver architecture for CDMA systems has both a good performance and a low complexity for IC implementation.