标题: | 里德所罗门解码器之通用型架构设计 Universal Arcdhitectures for Reed-Solomon Error-and-Erasure Decoder |
作者: | 张富科 Fuke Chang 张锡嘉 Hsie-Chia Chang 电子研究所 |
关键字: | 里德所罗门;Reed-Solomon |
公开日期: | 2004 |
摘要: | 里德所罗门码主要用来保护资料来避免在传输中可能发生的错误,它的数学演算主要是根据有限场(finite field)的运算。 里德所罗门码在许多应用上都有例子,譬如CD, DVD光碟机,cable modern以及DVB-T的系统。 然而在各种应用里,因应不同的规格要求,每种里德所罗门马有着完全不同的参数以及不同的有限场的定义和p(x)。 而以往的多模式设计,总需要花上许多的硬体和周期来处理不同有限场定义的问题。 因此本论文提出一个完全多模式的里德所罗门码解码器,它可以同时处理不同的参数包含可更正的错误和有现场的定义。 我们总共提出两种的架构,第一种架构主要支援最高有限场次方到10,第二种架构有限场次方到8。 除此之外,我们还应用一些小面积的设计考量于次方为八的架构,使得能够达到小面积的设计。 这两种架构都以0.13 1P8M的制程来实现,分别需要110K和53K个逻辑闸。根据模拟的结果,最快可以达到220MHz以及250MHz的工作频率。 Due to protecting the data form random error and burst error during transmission, Reed Solomon (RS) code has been widely accepted as the forward error correction scheme, such as xDSL, cable modem, and DVB-T. Because of the different RS specific parameters, a cost efficient RS decoder that can support various applications has practical importance to reduce the time-to-market and design costs. This thesis presents two universal architectures for Reed Solomon (RS) error-and-erasure decoder that can accommodate any codeword with different code parameters and finite field definitions. The first architecture can support the maximum degree to 10, and the second architecture can support to 8. The area efficient design approach is also considered in second architecture. Implemented with 1.2V 0.13□m 1P8M technology, the two decoders can operate at 220 MHZ and 300MHz and reach 2.2Gb/s and 2.4Gb/s data rate, respectively. The total gate counts of two decoders are 110K with core size 0.78mm2 and 54K with the core size 0.36mm2. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT009211659 http://hdl.handle.net/11536/67390 |
显示于类别: | Thesis |
文件中的档案:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.