可重複規劃的排程針對異質環境下系統晶片架構之研究

Abstract

隨著半導體製程技術的快速發展帶來了系統單晶片的設計潮流。 對IC設計者而言，如何有效率地整合最先進的元件和現有的資源來幫助設計、縮短設計週期，變得十分重要，尤其是在異質環境的系統晶片架構下，各個組成的部分都是相異性質的。 為了減輕系統晶片整合的複雜度，這篇論文針對動態排程方面，在異質環境的系統晶片架構下提供了一個可重複規劃的排程器。一般而言，一個系統晶片的應用通常可以被分成數個微小的工作，這些微小的工作為不可分割，且執行時間在被執行之前是未定的。 因此，有別於傳統的靜態排程，我們的研究使用Petri-Net Model來描述這些不同應用的動態行為；並針對異質環境下的系統晶片利用Petri-Net Model的動作方式我們建立出Petri-net Table(簡稱PN table)來達成控制整個資料流的計算方式和事件驅動的操作。 最後，本篇論文將舉實例來說明這個動態排程器可針對各種不同的DSP應用，只需要重新規劃而不需要重新設計，我們可以將它應用於異質環境的系統晶片架構下。

The System-On-Chip technology has been driven by the dramatic growth of semiconductor technology. How to efficiently integrate the state-of-the-art components and resources into a single chip and shorten the design cycle of SOC becomes crucial to IC designers. It is especially true for SOC consisting of dissimilar constituents, called heterogeneous SOC. To relieve the complexity of SOC integration, this thesis targets on dynamic scheduling and provide a reconfigurable scheduler for heterogeneous SOC. Normally, an SOC application can be divided into several atomic tasks. These atomic tasks are non-preemptive and their overall processing time can be non-deterministic. Therefore, instead of using the traditional static scheduling, our research uses Petri-Net models to describe the dynamic behavior of applications. Based on the Petri-Net computing, we propose a Petri-Net table (PN Table) to control the dataflow computing and perform the event-driven operation for heterogeneous SOC. As a result, this thesis illustrates that the dynamic scheduler is reconfigurable for DSP applications and can be applied for heterogeneous SOC architectures.