SOI-AWG 元件之設計與模擬

Abstract

近年來，隨著網際網路的蓬勃發展,傳輸頻寬的需求與日俱增，因此，可大幅提高傳輸頻寬之高密度分波多工 技術的相關研究與應用始在科技先進的歐美及日本快速而蓬勃的展開。其中以陣列波導光柵技術最容易達到多波 道數與窄頻道間距的功能，所以本論文即以矽在絕緣層的光波導結構來設計與模擬此AWG平面光波導元件。在本 論文中，分析各種DWDM技術的優缺點並詳細介紹AWG元件的基本工作原理，並使用可做3D運算的光波導數值 模擬軟體BeamPROP來輔助完成設計工作。在元件設計上，利用在輸入波導端設計拋物線波導結構將高斯分佈的 頻譜改善為平坦化分佈的頻譜，且在不同的輸出波導上加入不同寬度的漸變區，以達到輸出頻譜的損耗單一化。 我們可設計出128個波道數、頻道間距為0.4nm (50GHz)功能正確的SOI-AWG 波長多工/解多工元件且元件特性符合 商用規格。此外分析因製程誤差（如寬度、深度等）可能對頻道間干擾所造成的影響，最後討論溫度改變與極化 差異性對中心波長偏移的影響，使設計工作更完整。

In this paper we present our design and simulation results of array waveguide grating (AWG) devices based on the Silicon-On-Insulator (SOI) fabrication technology. Compared to other fabrication technologies like the Silica-on-Silcon technology, the SOI technology has the advantages of higher-functionality integration and lower fabrication cost. We have successfully designed SOI-based AWG devices with a flattened wavelength response by utilizing parabolic waveguide horns, Y-branch couplers, or Multi-Mode Interference (MMI) couplers which are placed at the entrance of the input slab waveguides. We obtain a 1dB bandwidth of 45 GHz and crosstalk < -50 dB. To reduce the channel non-uniformity we use different width tapers in each output waveguide. We have also simulated the impacts of the phase errors of array waveguides that are caused by the fabrication uncertainties. The impacts of the wafer surface roughness have also been taked into account in our simulation for completeness. Thes results should be helpful for the actual fabrication of the designed devices in the future.