針對長係數有限脈衝響應濾波器硬體實現且符合成本效益的摺疊技巧

Abstract

本篇論文針對有限資源實現長係數有限脈衝響應濾波器提出了兩種有效率摺疊硬體的演算法，其所採用的摺疊演算法是根據處理速率( Throughput )條件來做評估。在架構中使用少量的運算器，規劃其運作時序，就可分時完成工作，如此一來可以減少硬體中乘加運算器的數目，縮小硬體的面積。摺疊演算法非常適合於處理速率不需要很高的陣列硬體架構，尤其是對於陣列的運算單元個數會因規格的不同而有數目上變化的應用。利用推導成本函數來比較各種摺疊演算法在硬體實現上面積與功率消耗優劣，發現Parallel-In摺疊演算法在兩方面效能表現皆是最佳，並透過WCDMA規格實際實現各種摺疊演算法得到證明；最後，使用UMC 0.18μm 1P6M CMOS製程完成晶片下線。

This thesis presents two hardware efficient folding techniques for limited-resource implementation of long-length FIR filtering. Under the requirement of the throughput rate, we fold the FIR with the minimal number of processing elements (PEs) while the complexity of scheduler is low. The proposed folded architecture is highly scalable as the application parameters change.Cost functions are derived and these are used to address two related issues. The first issue focuses on memory requirements in folded architectures. The second is power consumption. The result of memory requirements and power estimation show that Parallel-In folding technique can turn out less memory area and power dissipation than do other folding techniques. Finally, the chip is implemented by using the UMC 0.18 μm 1P6M CMOS technology.