應用於音訊編解碼器之具成本效益數位訊號處理器

Abstract

近年來Sigma-Delta(Σ-Δ)技術運用在音訊處理可說是很常見的一種應用，原因就在於Σ-Δ調變器利用超頻取樣(Over-sampling)與雜訊塑造(Noise shaping)可以有效的降低類比電路的複雜度與準確度的要求。對於中低頻( <1 MHz)訊號，Σ-Δ調變器可輕易達到高解析度( >12位元)的目標，因此非常適合應用於音訊頻帶(20~20kHz)訊號處理。然而除了類比電路之外，在使用Σ-Δ調變技術中需要相對應的數位訊號處理器包含數位降頻濾波器(Decimation Filter)和升頻濾波器(Interpolation Filter)，其所需的硬體面積相對於類比電路而言是不分軒輊，甚至有可能更高，因此本論文便針對此部份加以討論以期降低其複雜度，其中我們提出了多種不同架構的降頻濾波器(使用於Σ-Δ類比/數位轉換(ADC))和升頻濾波器(使用於Σ-Δ數位/類比轉換(DAC))，來做成本效益的比較，並選取最低成本的架構，分別依照商業產器規格(TI和ANALOG DEVICE)來做硬體的實現，最後亦設計了一個不需使用乘法器的數位Σ-Δ調變器(使用於Σ-Δ DAC)，來達到低成本的要求。

Sigma-Delta (Σ-Δ) modulation technique is very popular in audio processing applications in recent years due to it can effectively release the demand of complex and high precision analog circuits by using over-sampling and noise shaping techniques. For low to medium frequency signals (<1MHz), Σ-Δ modulator can easily achieve the goal of high resolution (>12bit); as a result, it is suitable for audio band (20~20kHz) signal processing. Besides some simple analog circuits, the Σ-Δ modulation technique also requires the digital decimation filter and interpolation filter. However, the digital hardware area may be equal or even larger than the analog parts depending on the fabrication process. Hence this thesis focuses on reducing the complexity of the digital signal processor, and proposes a number of decimation filters (in Σ-Δ ADC ) and interpolation filters (in Σ-Δ DAC) with different architectures in order to evaluate their cost-performance ratios. According to the previous investigations, we select the lowest-cost architecture and implement the hardware that compiles with the commercial specifications (adopted from TI and ANALOG DEVICE) and we also design a digital Σ-Δ modulator (used in Σ-Δ DAC) that do not need any multiplier to achieve the goal of low cost.