IAM2000S微處理器內部記憶體控制設計與驗證

Abstract

由於晶片科技的蓬勃發展，快速增加晶片(IC)的電晶體數量，系統單晶片(System-on-Chip: SOC)的時代已經提前到來，而各種系統單晶片的架構，也不斷的推陳出新。在我們的解決方案中，以IAM2000S為核心，內涵記憶體管理系統(Memory Management Unit: MMU)，快取記憶體(cache)架構，整合AMBA AHB為系統匯流排，PCI為週邊匯流排；使其能夠被利用來發展嵌入式系統。 在快取記憶體的選擇上，採用哈佛的快取記憶體架構，它能有效的增加處理器內部資料流的頻寬。然而同時，記憶體管理單元與轉換緩衝器(Translate look-aside buffer: TLB)也會變成兩份；雖然增加了效率，這也使的設計複雜化，一套有系統驗證方式的需求，相形重要。 以位址與資料流為基礎的驗證觀念，可以應用於矽智財元件(IP)設計的驗證上。藉由使用自動比對驗證系統，有效地縮減了驗證內部記憶體控制的時間。在使用以位址與資料流為基礎的驗證方法後，我們可以保證的內部記憶體控制驗證品質。

The size of chips is doubled every eighteen months, according to Moore’s Law. Recent System-on-Chip (SOC) design and intellectual property (IP) integration further add up the IC transistor count and contribute to this ongoing change. The solution of the SOC design we provided is based on the IAM2000S (Information Appliance Microprocessor), included memory management unit (MMU), cache, AHB for system bus and PCI for peripheral bus. The IAM2000S SOC can be exploited to develop an embedded system. The Harvard cache architecture has been selected for internal cache memory architecture which is effective in improving the internal memory bandwidth. At the same time, the memory management unit is divided into data memory management unit (DMMU) and instruction memory management unit (IMMU), and so does TLB (translate look-aside buffer). As the internal memory control became complex a systematic verification is required. The concept of the address and data flow based verification can be employed in verifying some soft IP designs. The verification time of the internal memory control is effectively reduced by the auto-comparison verification system. The verification quality of internal memory control can be guaranteed after performing verification by the address and data flow based auto-comparison verification system.