Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Guo, Jyh-Chyurn | en_US |
dc.contributor.author | Yeh, Chih-Ting | en_US |
dc.date.accessioned | 2014-12-08T15:09:00Z | - |
dc.date.available | 2014-12-08T15:09:00Z | - |
dc.date.issued | 2009-08-01 | en_US |
dc.identifier.issn | 0018-9383 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TED.2009.2022679 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/6847 | - |
dc.description.abstract | A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance C(of) dominates around 25% of the intrinsic gate capacitance (C(gint)) in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor C(of)/C(gint) above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | MOSFET | en_US |
dc.subject | nanoscale | en_US |
dc.subject | parasitic capacitance | en_US |
dc.subject | 3-D capacitor model | en_US |
dc.title | A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TED.2009.2022679 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON ELECTRON DEVICES | en_US |
dc.citation.volume | 56 | en_US |
dc.citation.issue | 8 | en_US |
dc.citation.spage | 1598 | en_US |
dc.citation.epage | 1607 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000268282400006 | - |
dc.citation.woscount | 5 | - |
Appears in Collections: | Articles |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.