IAM2000S微處理器之快取記憶體與寫入緩衝器的設計與實作

Abstract

近年來，由於系統晶片(System-on-Chip,簡稱SoC)的蓬勃發展，加上對矽智產元件(IP)重覆使用的觀念，基於這樣的設計發展的趨勢，本論文提出了一個在既有的微處理器核心架構前提下，整合週邊環境和外部匯流排成為一個矽智產元件的設計和實作，為目前業界普遍採用的方法。 本論文是設計出具有信號處理能力的嵌入式微處理器IAM2000S的快取記憶體架構，結合記憶體管理單元和寫入緩衝器，讓IAM2000S能夠從快取記憶體得到正確的指令和資料。在設計架構和寫入策略以及取代策略等不同設計考量下，如何設計一個具有最佳效能且相容於IAM2000S微處理器架構是本論文的目標。 除了在硬體架構的設計之外，輔助以設計自動化工具來模擬和分析快取記憶體和寫入緩衝器的正確性和效能評估，整合IAM2000S成為一個完整的微處理器。

Recently, basis the rapid development of System-on-Chip (SoC) and the concept of reusing Intellectual Property (IP), the thesis propose the design and implementation of architecture with an existent microprocessor core and integrated peripheral environment and external bus to be an IP. This is commonly used in ICs industry. In this thesis, we propose the design of cache architecture for an embedded RISC microprocessor with DSP capability, IAM2000S. With the integration of memory management unit and write buffer, IAM2000S can access the instructions and data fast and correctly. In the different consideration of cache architecture, write policies and replacement strategies, the major objective is to design a memory access system with best performance and compatible with IAM2000S. Besides the design of hardware architecture, we simulate and analysis the accuracy of cache and write buffer by computer-aid-design tool. We provide the integration methodology for the IAM2000S to be a complete microprocessor.