高效能且低雜訊之電源管理晶片實現

Abstract

本論文的內容主要是要設計一個適用於動態電壓調整的直流轉直流電壓轉換器，現今由於可攜式資訊設備的廣泛應用，使的低電壓低功率省電IC的發展將愈為重要，這將促成電源、電池、與SOC進一步的整合，引發高功率密度的智慧型電源技術的發展。然而，除了必須著重於電源供應的功率消耗低之外，如果能有效地使用能源，也就是利用電源管理的方法，更能達到真正省電的效果，動態電壓調整 (DVS) 是一種有效率的電源管理方式，由於其輸出電壓會不斷改變，因此，在設計上和傳統的固定電壓輸出的穩壓器有所不同。本論文設計一個負載電流偵測器，將系統分成輕載和重載的穩壓模式，使其分別操作與PWM和PFM模式來達到最佳的功率效能轉換，又為了避免輸出電壓受到負載的影響而震盪，使得輸出電壓峰對峰值過大，因此，我們將利用低壓降線性電壓穩壓器 (LDO) 的低壓降優越性，只需要約0.3v以內的跨壓即可，將PWM / PFM的輸出電壓再當成LDO的輸入電壓，透過這樣再做一次穩壓的動作，將負載輕重對輸出電壓的影響降到最低，並使輸出電壓達到更高的穩定度。

The content of this thesis is to design a high-efficiency DC-DC converter for dynamic voltage scaling (DVS) which is efficient power management because of it can dynamic adaptive supply voltage with the desired voltage of equipment system. In the recently, power consumption becomes the important issue in the CMOS circuits design, because many portable electronic equipments demand low-power and highly-efficiency designs to extend battery life. So the low-power design techniques are developed to reduce power consumption. In this thesis, the control method is base on the dynamic switching the PWM and PFM modes. By using the current detector to sense the load current, we use the PWM mode to operate in the heavy load and the PFM mode to operate in the light load. Then, the system will have high efficiency for different load condition. However, the output voltage ripple is affected by the variable output load. In order to avoid the high output ripple, the linear regulators, which have very small output ripple and low output noise, are connected in series between the switching regulators and the output terminal of the system. Beside, the system can maintain the drop voltage about 0.3 volts between the input and output voltage of the low dropout regulators to decrease the power consumption in the linear regulator. Then, a highly-efficiency and low noise converter is presented and can be used in low noise RF circuits.