數位類比轉換器之內建測試電路研究

Abstract

由於超大型積體電路技術的快速進步，測試類比混合電路變得越來越困難。在這篇論文中，我們採用類比加法器把電壓量測轉換到時間量測來完成對數位類比轉換器所提出的內建測試方法。為了保證測試的精準度，在電路中會加上測試電路來針對製程容忍度所產生的誤差來作校正。此方法在八位元數位類比轉換器當待測電路下得到驗證。

Testing analog/mixed-signal circuitry becomes more and more difficult due to the rapid advance of the VLSI technology. In this thesis, we propose a new BIST scheme for testing Digital-to-Analog Converters (DACs) by adopting an analog summer to transform the voltage measurement into the timing measurement. To guarantee the accuracy of testing, calibration circuits are added to calibrate errors on the testing circuit caused by process tolerance. The scheme has been demonstrated by using an 8-bit DAC under test.