标题: 数位类比转换器之内建测试电路研究
A New BIST Scheme for Digital-to-Analog Converters
作者: 陈冠勋
Guan-Xun Chen
李崇仁
Chung-Len Lee
电子研究所
关键字: 类比加法器;制程容忍度
公开日期: 2001
摘要: 由于超大型积体电路技术的快速进步,测试类比混合电路变得越来越困难。在这篇论文中,我们采用类比加法器把电压量测转换到时间量测来完成对数位类比转换器所提出的内建测试方法。为了保证测试的精准度,在电路中会加上测试电路来针对制程容忍度所产生的误差来作校正。此方法在八位元数位类比转换器当待测电路下得到验证。
Testing analog/mixed-signal circuitry becomes more and more difficult due to the rapid advance of the VLSI technology. In this thesis, we propose a new BIST scheme for testing Digital-to-Analog Converters (DACs) by adopting an analog summer to transform the voltage measurement into the timing measurement. To guarantee the accuracy of testing, calibration circuits are added to calibrate errors on the testing circuit caused by process tolerance. The scheme has been demonstrated by using an 8-bit DAC under test.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900428060
http://hdl.handle.net/11536/68754
显示于类别:Thesis