標題: 極低介電常數材料在製程與整合之研究
Study on Integration of Ultra Low-K Material
作者: 林宗衛
Zong-Wei Lin
吳啟宗
張鼎張
Dr. Chhi-Chong Wu
Dr. Ting-Chang Chang
電子研究所
關鍵字: 極低介電常數材料;low-k
公開日期: 2001
摘要: 摘要 隨著半導體技術的進步,元件的尺寸不斷的縮小,並且進入了深次微米的領域內。為了增加積體電路的性能,降低導線的線寬和增加金屬導線層的數目,便成為超大型機積體電路技術所採用的方式。但此時,訊號傳遞的時間延遲和高功率的消耗便成為很嚴重的問題,大大降低了元件的表現性。為了解決此問題,便引入了低介電材料和銅導線來取代傳統的製程。在眾多的低介電材料中,PPSZ (porous organo-silsesquiazane)薄膜,是其中極具發展潛力的一種材料。在本論文中,將對此材料的物性、熱穩定性及電性進行探討,並討論與銅導線整合,結果發現此材料不但有極低的介電常數,而且有很好的熱穩定性,並且發現與銅整合的漏電機製是Schottky-like。 低介電常數材料目前發展包括:有機類(organic)和無機類(non-organic)兩大類材料,但這兩大類low-k材料應用於製程上卻產生一些新問題,其中一個非常嚴重的問題是去光阻的灰化過程(ashing process),因為灰化過程中使用的氧電漿會對low-k薄膜造成很大的傷害,使薄膜的特性變差,介電常數上升,漏電流增加,薄膜失去好的絕緣性,這會讓製程的良率下降。 E-beam微影的方法正是解決此問題的關鍵技術,低介電材料經過E-beam的曝光,使照射到的部份固化,便可以利用溶濟將未固化的部份洗去,進而得到我們想要的圖型,這就是利用E-beam direct patterning的方式,最後我們將探討溶劑對薄膜的影響,發現E-beam的方法是可行的,這樣便可避免灰化過程。
Abstract As the feature of the integrated circuit (IC) is scaled down, the resistance and capacitance of multilevel interconnect are increased due to the thinner metal wires and shorter distance between them. The interconnect RC delay and power dissipation will be increased and become an issue of performance. Therefore, conductors with lower resistivity and dielectrics with lower dielectric constant are thus deeply needed for ultra-large scale integrated circuits (ULSIs) generation. In this thesis, we use new low-k dielectric PPSZ (porous organo-silsesquiazane, k=2.2) to replace traditional SiO2 (k=4.0). In order to be useful, the intrinsic properties of new low-k dielectrics such as fundamental physical, electrical, thermal stability of the spin on glass (SOG) have been found. And we used PPSZ as the insulator and Cu as the conductor to evaluate the electrical properties of PPSZ. During the integration process, we must experience the photoresist (PR) removal process. The most of PR are removed by utilizing O2 plasma process. The low-k films will be degradged by the damage from oxygen plasma during photoresist ashing process. The leakage current and dielectric constant will be increased. E-beam lithography technology will solve these issues and it will be a useful tool in advance IC fabrication. The advantage of the E-beam exposure is direct patterning, avoids the issues during the etching and photoresist removal process. Then we use solution to develop the films, and get the pattern that we want. At least, the effect of solution has been investigated.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT900428065
http://hdl.handle.net/11536/68759
顯示於類別:畢業論文