鎖相迴路內建頻率飄移測量電路之研究

Abstract

鎖相迴路目前被廣泛地運用於許多高速電子系統中，可當時脈調整器，亦可當頻率同步器。輸出週期變動量對於鎖相迴路是一個非常重要的效能指標，它是輸出訊號與理想訊號時間差的變動，有可能領先，也有可能落後。過大的變動量在通訊系統中，可能造成資料的流失，在微處理機系統中，可能造成計算上的錯誤。關於輸出週期變動量測量問題，需要一個準確度高達微微秒的測試機器，才能求得較為準確的值，但是卻提高了測試成本。吾人則提出利用一簡單設計，內建於測試電路中，將時間差轉換成數位訊號，並由一連串的數位資料求得輸出週期變動量，如此由一般的邏輯測試機器就可以達到測量目的，大大地降低測試成本。未來在單晶片系統中亦可使用此內建電路設計量測輸出週期變動量。

Phase-Locked Loops (PLL) are used in many high-speed electronic systems. It can be employed as the clock recovery and the frequency synthesizer. Jitter is an important parameter in Phase-Locked Loops specifications. It can be defined as the deviations in a clock output transition from their ideal position. The deviation can either be leading or lagging the ideal position. In a communication system, a larger jitter affects data correctness. And in a microprocessor system, a larger jitter results in wrong computation. For the jitter measurement, we need a high-resolution (pico-second) instrument in the Automation Test Equipment (ATE) to acquire more accurate values. In the thesis, we propose a simple, built in the circuit under test, design to transfer timing difference to the digital signal. Jitter values are obtained from several digital words. As a result, a general logic ATE can do the jitter measurement and the cost of test can be reduced. This design can also be used in an SOC design to measure jitter.