鐵電薄膜介電特性之新型態量測方法與鐵電記憶場效電晶體之元件模型

Abstract

在這篇博士論文中，鐵電材料的介電特性，量測方法，元件應用與元件模擬是探討的主題。討論的材料主要是針對鈣鈦礦結構，包含鈦酸鍶鋇，鈦酸鍶,，鉭酸鍶鉍與鉭酸鉍鑭的基本介紹與元件應用。本文首先會介紹鐵電材料的基本物理原理。其後會分別介紹鐵電材料應用在”可調鐵電微波元件”，”高介電閘極氧化層”與”鐵電隨機存取記憶體”的原理與設計。為了提供比較完整的觀念，包括元件，材料與電路設計都會一一探討。文中也會回顧一些重要文獻，以及相關領域的重要議題。 這篇論文雖然以探討鐵電材料為主，但是探討的重點主要是針對鐵電材料的高頻量測技術以及元件模擬，而不是薄膜製成。首先，我會介紹鈦酸鍶鋇成長於氧化鋁基板的微波特性。將共平面波導管製作於薄膜上，可以藉由量測微波S-參數得到薄膜的介電係數與介電損耗。量測時首先需經由精確的”穿透-反射-傳輸線”校正，得到扣除寄生與阻抗不匹配之效應，然後藉由保角映象方法求得精確的薄膜介電係數與介電損耗。這種方法有別於傳統的薄膜電容量測，而是採用了微波傳輸線方法，可以扣除高頻微波量測時許多寄生效應。這種量測技術相當於一種新型態的鐵電/高介電薄膜之介電特性微波頻譜儀。 接下來，利用這種介電特性微波頻譜儀可以來研究高介電閘極氧化層。對於大部分的高介電閘極氧化層，都有一個共通存在的問題，就是會有一個薄的中間層會介於矽與閘極氧化層之間。這個中間層通常是因為交互擴散或矽的氧化而形成的，它會增加等效氧化層厚度，並造成能陷(trap states)，使得高介電閘極氧化層的性能降低。這個中間層通常是接近於二氧化矽的矽化物(silicate)加上許多擴散進來的離子，因此這個中間層的介電係數很難被決定。然而，目前仍然沒有方法可以比較準確的求得這個中間層的介電係數。在這個研究中，我會採用微波傳輸線量測方法，搭配金氧半電容的特性量測，求得鈦酸鍶鋇閘極氧化層以及中間層的介電係數。在這個量測中，還發現傳輸線的損耗和電壓的關係與介面能陷有密切關連。為了證明這個觀點，利用非晶矽薄膜沈積於矽晶片上，量測它的特性。這個實驗結果發現，用傳輸線方法，不僅可以準確的量測中間層的介電係數，還可以觀測介面能陷的數量，是一種對於材料分析很有用的新工具。 前述量測的結果證明了鈦酸鍶鋇薄膜的介電係數即使到了20 GHz仍然保持不變，有別於傳統的薄膜電容量測結果。這啟發了改進傳統的薄膜電容量測方法的動機。因此發展了一種改進的雙頻率電容量測方法應用於高介電閘極氧化層。對於大部分的高介電閘極氧化層其電容量測在高頻時很容易出現頻散效應。這個頻散效應通常出現在數百千赫(several 100 kHz)以上，造成決定介電係數與等效氧化層厚度(EOT)的困擾。然而，依照前述的實驗結果可以發現，其實高介電材料即使到微波頻段仍然沒有明顯的頻散效應，因此電容量測的頻散效應該是其他電路的因素而不是材料本身的因素造成的。為了解決電容量測的頻散效應，我提出了改進式的雙頻率電容量測方法，這個方法是用等效電路模型來解釋電容量測，包括了內在電容，損耗正切(loss tangent)，串連電阻與串連電感。使用雙頻率的電容量測可以決定這些參數。當以鈦酸鍶閘極氧化層做實驗，翠取出來的內在電容和頻率無關，同時翠取的損耗正切，串連電阻與串連電感與頻率和電壓無關，證明了這個方法的一致性與準確性。另外，高介電閘極氧化層的損耗正切可以被決定，這對於高介電閘極氧化層的材料分析很有幫助。 本文也將探討鐵電記憶場效電晶體(FeMFET)之元件模型。最近，非揮散性的單電晶體鐵電記憶體(1T FeRAM)獲得了廣泛的重視，因為它可以允許非破壞性讀取以及高密度積集化。這個單電晶體鐵電記憶體主要是由鐵電記憶場效電晶體(FeMFET)所組成，類似於傳統的金氧半場效電晶體，不同的是，閘極氧化層是以鐵電材料取代，利用儲存的極化方向調變鐵電記憶場效電晶體的初始電壓(threshold voltage)，在汲極(drain)量測電流的差別而鑑別其記憶狀態。儘管這種新型態元件的重要性，這種元件仍然缺少精確的元件模型。在這一章裡，我將會發展一套新的理論計算方法，鐵電記憶場效電晶體包括金屬-鐵電-絕緣-半導(MFIS)以及金屬-鐵電-金屬-絕緣-半導(MFMIS)的結構都會被廣泛探討。元件的電流-電壓以及電容-電壓的特性曲線在各種不同的材料以及元件參數下都可以被模擬。模擬的結果和實驗數據非常吻合，證明了這個理論方法的正確性。這個理論模擬的重要性在於能夠提供設計準則(design rules)，用來最佳化元件特性，這對於單電晶體鐵電記憶體的設計有很大的幫助。 最後，我會對於我的博士論文的研究結果做一總結。隨後，鐵電可調微波元件，高介電閘極氧化層以及鐵電記憶體相關的一些具有可行性的研究主題將會被討論。

In this thesis, several topics concerning the dielectric properties, device applications, device simulations and measurement techniques of ferroelectric thin films such as Ba0.5Sr0.5TiO3 (BST), SrTiO3 (STO), SrBi2Ta2O9 (SBT) and (Bi,La)Ta2O9 (BLT) are studied. Firstly, I will briefly introduce the fundamental physics of the ferroelectric materials. Electrical and material properties of these ferroelectric thin films are discussed. The applications of these materials such as microwave tunable devices, high-k gate dielectrics and ferroelectric random access memory (FeRAM) are introduced. Topics including devices, materials, processes and circuit schemes of these applications will be described in order to provide the technical backgrounds of these subjects and an understanding of the motivation of this thesis. The studies in this thesis are mainly focused on the high-frequency measurement techniques and device modeling of ferroelectric materials, rather than the thin film processes. Firstly, the dielectric properties of BST thin films deposited on sapphire wafer were investigated in chapter 3. Coplanar waveguides (CPW) transmission lines were fabricated on the top of the BST thin films and S-parameters of the CPW transmission lines were measured by the network analyzer. Thru-Reflect-Line (TRL) calibration together with the conformal mapping formulas were employed to accurately measure both the dielectric constants and loss tangents of the BST thin films at frequencies ranging from 200 MHz to 20 GHz. I have developed the measurement procedures in detail, and the results imply that this method serves as a new kind of microwave spectroscopy for measuring the dielectric dispersion of the ferroelectric/high-k thin films. Next, this new kind of microwave spectroscopy can be extended to investigate the high-k gate dielectrics, as described in chapter 4. For most high-k gate dielectrics, there inevitably exist thin interfacial layers between the silicon and the dielectric layers. These thin interfacial layers are often naturally formed by the interdiffusion during the high-temperature growth of high-k gate dielectrics. In addition, the lattices mismatch between the dielectric and silicon surfaces also causes thin amorphous layers between them. These interfacial layers play an important role because they greatly degrade the performance of the high-k gate dielectrics. Many studies used multi-thickness method to measure the dielectric constants of the interfacial layer. However, this method provides only a rough estimate. In this study, I combined the microwave spectroscopy together with the CV measurement to measure both the dielectric constants of the BST gate dielectric and the thin interfacial layers. In addition, I have discovered an interesting phenomenon of the behavior of insertion loss versus bias voltages. This phenomenon is related to the effect of interface trap states. For more illustration, poly silicon thin films with high trap densities were measured to justify this assumption. The results indicate that this method can be used to measure the dielectric constants of the high-k gate dielectrics and interfacial layers and qualitatively investigate the densities of interface trap state. The measurement results of BST thin films in both chapter 3 and 4 show that the dielectric constant of BST does not change with respect to the frequency even up to 20 GHz, which is quite different from the results in the conventional capacitor measurements. This result inspires the motivation of improving the capacitance measurement technique, as described in chapter 5. The dielectric constants of high-k gate dielectrics measured by the CV measurement often show large frequencies dispersion of the capacitance measurement at high frequencies (> 100 kHz). This phenomenon may be due to the extrinsic parasitic effect rather than the intrinsic dielectric properties of the materials. I have proposed an improved method of the Yang and Hu’s two-frequency method. In this method, the intrinsic capacitance, loss tangent, series resistance and series inductance can be extracted by measuring the MOS capacitor at two different frequencies. STO high-k gate dielectrics were fabricated and the experimental results of CV measurements showed that the extracted parameters are independent on bias voltages and frequencies, indicating this method is self-consistent with the assumption of this equivalent circuit model. This method can be incorporated in the routine robust CV measurement of high-k gate dielectrics. Next, the device modeling of the ferroelectric memory field effect transistor (FeMFET) is discussed in chapter 6. Recently, the one-transistor ferroelectric random access memory (1T FeRAM) has gained intensive interest because it can provide very high-density non-volatile memories with non-destructive read-out operation. The 1T FeRAM is composed of the FeMFET, where the ferroelectric materials are used to replace the gate oxide of the MOSFET. The polarization in both directions stored in the ferroelectrics can change the threshold voltages of the transistors, and in turn the drain current difference of the two states can be identified as logical states “1” or “0” in a memory. In chapter 6, I intend to develop a detailed model for the device simulation of the FeMFET. Both metal – ferroelectric–insulator–semiconductor (MFIS) and metal–ferroelectric–metal-insulator– semiconductor (MFMIS) capacitors and the associated transistors were investigated. The parameters used in the simulation were close to those of the SBT and BLT system. Electrical characteristics of the devices including the C-V, ID-VG and ID-VDS plots can be simulated by this model, and the simulation results were close to the experimental data. Finally, the overview of the device performance, reliability issues such as retention time and fatigues, charge injection and short channel effects will be discussed. At last, I will summarize the results of my studies in this thesis. Several suggestions of the further studies of microwave tunable devices, high-k gate dielectrics and FeRAM will be proposed.