以DSP 為基礎的IS-2000 接收機架構

Abstract

本篇論文著重於IS-2000 上行鏈路接收機架構的DSP 實現，我們不僅使用電腦程式來模擬IS-2000 在上行鏈路下接收機性能的表現，亦使用德州儀器公司的C6201 DSP 晶片來達成硬體實現。IS-2000 傳送端使用混合式相位鍵移 (HPSK) 來降低鋒均比(peak-to-average ratio)並增進前端功率放大器的效率。IS-2000 系統同時也使用多重碼分碼多工 (Multi-Code CDMA) 機制以符合IMT-2000 (International Mobile Telecommunications Systems-2000) 高速資料傳輸的要求。在傳送過程中，我們使用 SRRC (Square-Root Raise-Cosine) 波形來傳送資料，因此導入了符元間干擾(Inter-symbol interference)的效應。 在IS-2000 接收機部分，我們使用最大比率結合(Maximal Ratio Combining)犁耙式接收機(RAKE receiver) 來減輕因為通道衰退效應(fading channel effect)所導致的系統性能降低。我們使用二階的Butterworth 低通濾波器來估計因為通道效應所引起的相位失真，並作為最大比率結合犁耙式接收機的加權值。 為了實現整個接收機架構，我們使用德州儀器公司的C6201 定點(fixed-point)DSP 晶片來實現IS-2000 接收機架構。最後我們並比較電腦軟體模擬的結果與DSP 硬體實現的性能表現，來證實兩者非常接近。

This thesis addresses issues on implementing the receiver of IS-2000 reverse link. We estimate the performance of an IS-2000 reverse link receiver by both computer simulations and DSP-based realization. The transmitter of the IS-2000 system uses Hybrid Phase Shift Keying (HPSK) to reduce the peak-to-average e?ect and enhance the e?ciency of the front-end power ampli?er. IS-2000 also uses a multi-code code division multiple access (Multi-Code CDMA) scheme. This scheme makes high data rate transmission required for International Mobile Telecommunications Systems-2000 (IMT-2000) possible. Square-Root Raise-Cosine (SRRC) chip pulse is used to produce compact signal spectrum but at the same time introduces inter-symbol interference (ISI) in a multipath fading environment. The RAKE receiver we investigate uses the maximum ratio combining (MRC) to mitigate the performance degradation caused by the channel fading e?ect. A crucial part of an MRC RAKE receiver is the channel estimator. We use a pair of low-pass Butterworth ?lters at each ?nger to estimate the associated complex channel distortion. To realize our design, we employ TI's ?xed-point DSPs (TMS320C6201). Detailed implementation issues such as bu?er management, scheduling and C code optimization are discussed and performance examples are given. We compare the performance predicted by computer simulation and that by hardware (DSP) and ?nd both yield almost the same result.