W-CDMA通道解碼器與空時犁耙接收器之FPGA與DSP實現

Abstract

W-CDMA (Wideband Code Division Multiple Access)為第三代行動通訊標準之一，它利用分碼多重進接技術達到高資料速率及高系統容量之目標，並具有彈性頻寬及多媒體服務等特性。在本論文中，吾人以Aptix® MP3C為發展平台，整合DSP (Digital Signal Processor)及FPGA (Field Programmable Gate Array)，實現W-CDMA上鏈路接收機架構。DSP具有高速數值運算能力，可提供即時之訊號處理；FPGA為可程式化之數位邏輯電路，可提供彈性設計及快速的電路驗證；而Aptix® MP3C為一具高度整合性之雛型系統，它結合了Explorer軟體及邏輯分析儀，可提供吾人極為便利之系統發展及驗證。在本論文中，吾人將探討W-CDMA接收機之波束形成器、空時犁耙接收器及迴漩碼解碼器等。以波束形成器結合犁耙接收器可達到干擾消除之目的，以迴旋碼解碼器將錯誤的資料位元改正，則可使系統效能增加。吾人於系統設計過程中，引入軟體無線電之概念，適當規劃DSP及FPGA之工作分派，並以軟體程式調整系統參數，使系統功能更具彈性。

W-CDMA is one of the major standards for third-generation mobile communications. It employs the code division multiple access technology to achieve high data rate and high system capacity, and provide flexible bandwidth and multimedia services. In this thesis, we will use the Aptix® MP3C system as the hardware development platform, which integrates DSP and FPGA, to realize the W-CDMA uplink receiver. DSP can offer high speed numerical operations, which is suitable for real-time signal processing. FPGA is a programmable logic device, which offers flexible circuit design and quick verification. Aptix® MP3C is a highly integrated prototyping system, which integrates the Explorer software and Logic Analyzer, and provides convenient system development and verification. In this thesis, we will focus on the design of the beamformer, space-time RAKE receiver and convolutional decoder. The beamformer together with the RAKE receiver can cancel the multiple access interference, and the convolutional decoder can correct data errors to gain system performance improvement. Besides, with the concept of software defined radio incorporated, we can properly assign jobs to DSP and FPGA, and achieve system flexibility by software defined reconfiguration of system parameters.