應用於DCS-1800之分數型頻率合成器設計

Abstract

本論文主要探討整數型(Integer-N)和分數型(Fractional-N)頻率合成器兩者之間的差異性，針對分數型(Fractional-N)頻率合成器設計中，討論分數突波的原因及改善方法，此合成器採用具有快速鎖頻、與低分數突波特性頻率解析度為0.0596 Hz之25位元三階ΣΔ調變器架構及一8模除頻器，並利用可程式陣列邏輯（FPGA）將數位電路加以實現﹔頻率合成器中所要使用到數位電路如相位檢測器、可程式計數器和ΣΔ調變器，亦有詳細設計﹔可程式計數器的設計中，可在結束位元件檢測電路中加上一D型正反器，提高整體工作頻率，並利用TSMC 1p4m 0.35微米金氧半製成加以實現。

In this thesis, a fractional-N frequency synthesizer wih improved fractional spurs is studied. It employed the 25 bits third-order sigma-delta modulator technique to achieve low fast settling time, low fractional spurs and 0.0596 Hz frequency resolution. The third-order sigma-delta modulator as well as eight mode divider are realized on FPGA. The differences performances between Integer-N and fractional-N frequency synthesizer are indicated. The digital circuits such as phase frequency detector, programmable counter and sigma-delta modulator are also designed. The operating frequency of programmable counter is enhanced with extra added a D-flip-flop structure. The programmable counter are fabricated by TSMC 0.35um CMOS 1p4m technology.