利用源極電感的串疊式低雜訊放大器在Giga赫茲的設計與電路實現

Abstract

在這篇論文研究中, 討論了以源極電感和閘極電感做為輸入阻抗匹配, 以串疊式電晶體為架構的低雜訊放大器。並且以CMOS 0.25μm 的製程, 實作一個2.4GHz 單端低雜訊放大器, 及2.4GHz 差動式低雜訊放大器。在使用電路板的量測中, 積體電路以外的高頻寄生效應, 如積體電路到電路板的打線和電路板的拉線等等, 對於積體電路的影響較難估計, 以電路板的量測並不適當。在使用on-wafer 的量測上, 由於支援儀器的限制, 所以只做單端電路的量測。實際量測到差動式LNA的半電路, S11為 -33.6dB at 2.7GHz , S21為 7.5dB at 2.4GHz , input P1dB為 0dBm at 2.4GHz , input IIP3為 10.3dBm at 2.4GHz , NF為 3.91dB at 2.4GHz 。Cascode LNA with source degeneration 的架構在2.4GHz有不錯的效果, 在佈局及量測上需要多考慮高頻寄生效應。

A low noise amplifier using a gate inductor and a source degeneration inductor for input matching and with the cascode topology is discussed. A 2.4GHz single-ended low noise amplifier and a 2.4GHz differential low noise amplifier using CMOS 0.25μm process are implemented. In the on-board measurement , the high frequency parasitic effects outside the on-chip circuit, such as bond-wire effects from the on-chip circuit to PCB and micro-strip lines on the PCB, are difficult to estimated. The on-board measurement is not appropriate for LNA. In the on-wafer measurement, only single-ended circuit measurement is available because of the limitation of the measure apparatus. The measure results of the half-circuit of the differential LNA is as follows : S11 is -33.6dB at 2.7GHz , S21 is 7.5dB at 2.4GHz , input power of P1db is 0dBm at 2.4GHz , input power of IIP3 is 10.3dBm , and the noise figure is 3.91dB at 2.4GHz. The topology of the cascode LNA with source degeneration has good performance at 2.4GHz. And the high frequency parasitic effects should be considered in layout and measurement.