智慧型直接記憶體存取器設計

Abstract

數位訊號處理在現代科技生活上是非常重要的研究領域，舉凡通訊、娛樂到日常生活所需，都脫離不了數位訊號處理的範疇。在消費性電子產品的高度需求下，使用數位訊號處理器除了著重運算效能外，對成本的要求更為嚴苛。高階數位訊號處理器的成本相當高，若需降低成本而採用低階處理器去獲得相同的效能，勢必需要更高的時脈與更高的功率消耗。為了使一般通用型處理器達到數位訊號處理器的效能，使得通用型處理器的效能更為強大，本論文提出一個智慧型直接記憶體存取（DMA）控制器，以輔助處理器提升效能及傳輸效率。智慧型DMA控制器設計以傳統DMA傳輸模式設計加上支援四種定址模式，能夠有效選取傳輸資料區塊，降低傳輸的頻寬及處理器的負擔。它特別的設計特色是：（1）擁有內建乘加運算器搭配定址模式，可支援雙通道資料記憶體向量運算，協助處理器處理大量且具有規則與繁雜的數位訊號；（2）支援周邊輸出入匯流排，使得周邊擴充更有彈性；（3）內建乘加運算器僅僅增加10%的硬體成本，卻能使得處理器的效能大幅躍進。本論文設計一個智慧型DMA控制器，並整合於已開發的通用處理器核心上，成為一顆等同數位訊號處理器（DSP-like）的晶片。此晶片採用UMC 0.18μm 製程，以Cell-based方式設計，晶片面積約2.3x2.3 mm2，預估最大操作頻率在100MHz。

In recent years, digital signal processing plays an important role in our life, such as communication, entertainment and daily necessities. Under the high requirement of consumer electronics, expecting high performance, the cost requirement for a digital signal processor (DSP) is quite severe. Because the cost of a DSP is very high, if a general-purpose processor is used to reach the efficiency like a DSP, it will claim the higher clock rate and power consumption. In order to reach DSP-like performance of the processor, this thesis investigates a novel smart DMA controller to assist the processor to improve the performance and the transmission efficiency. Based on the traditional DMA, the smart DMA supports four kinds of addressing and transmission types so that it can select the region of valid data to reduce the bandwidth of transmission and the load of the processor. The features of smart DMA design are as: (1) it has a built-in multiplication-and-accumulation (MAC) which processes mass and regular data computation. Moreover, it has two channel controllers which can access two memories and perform vector operations at the same time; (2) it supports the peripheral I/O bus and it is flexible to expand I/O devices; (3) the cost of built-in MAC only increases 10%, but it can greatly improve the performance of the processor. This thesis represents the design of smart DMA integrated into the developed processor core, and then it becomes a DSP-like processor chip. The chip has been integrated in the total area of 2.3×2.3mm2 by using UMC 0.18μm CMOS technology and fabricated via the National Chip Implementation Center (CIC). The maximum clock frequency is 100MHz with a single 1.8V supply.