銅及多孔性低介電常數材料的製程整合研究

Abstract

在極大型積體電路中，隨著元件尺寸的縮小，電阻電容的時間延遲及訊號傳遞不良等問題也越顯突出，為了改善這些問題，以銅取代鋁作為中間連接導線的材料以及選用低介電常數材料取代傳統二氧化矽作為隔離層的方式已成為時勢所趨。 為了克服銅金屬容易擴散的問題，勢必需要在銅與矽基材之間鍍上一層具有高溫熱穩定性、良好界面接合性以及低電阻係數的擴散障礙層，來達到抵抗銅原子擴散以及低功率消耗的目的。本研究選用氮化矽鉭作為擴散障礙層，並藉由經過高溫退火後片電阻值的變化、X光的繞射分析，以及二極體接面漏電流的測試等，來評估此擴散障礙層的性質。結果發現在氮流量比為20%時的電阻率為最低，而厚度在10 nm的情況下其熱穩定性可以達到650°C以上的高溫，在二極體接面漏電流的表現上經過600°C退火1小時後可以維持在10-6A/cm2的漏電流密度。 在目前廣受研究的低介電常數材料當中，利用中孔洞分子篩技術所製備的低介電常數材料薄膜由於具有熱穩定性佳，與傳統製程類似，以及可藉由調整孔洞大小改變材料本身之介電常數等優點，因此具有相當大的潛力。本研究選用台大化工製程實驗室所開發出來的低介電常數薄膜來作為與矽基材間的隔離層，期望改善並簡化其製程，利用低功率氧(O2)電漿在數秒內將有機模板分子移除，或是使用真空爐管在較低溫度下將有機模板分子抽離，企圖取代一般冗長而高溫(400°C)的鍛燒過程；另外，利用氫氣(H2)電漿進行表面處理以取代HMDS表面改質的方式也是本研究的要點之一。結果顯示氧電漿確實可移除模板分子，但並不能夠得到低介電常數的薄膜，而以真空爐管在高真空下加熱抽氣的方式並無法將模版分子自薄膜中移除；另外，以氫氣電漿來作表面改質並不成功。 為了整合製程，本論文也對barrier/SiO2/Si及Cu/barrier/SiO2/Si的結構進行熱循環與退火對其阻值及應力大小的影響探討，藉由X光的繞射分析、表面粗糙度的鑑定，以及穿透式電子顯微鏡的觀察，來對應力遷移現象的機制做較完整的描述。

As the devices become smaller and dimensions decline to sub-micron scale, the performance of integrated circuits will be significantly limited by the interconnect RC time delay. To alleviate these impacts, copper and low dielectric constant materials are used to replace aluminum and silicon oxide as the conduction and dielectric layers in metallization system. Since copper diffuses fast in silicon substrate, a diffusion barrier with good thermal stability, contact resistance, and low resistivity is needed in Cu/Si contact system. Reactively sputtered Ta-Si-N layer was chosen as diffusion barrier in this study. Barrier capability against Cu diffusion was evaluated by sheet resistance, x-ray diffraction (XRD), transmission electron microscopy, and leakage current of junction diode. The Ta-Si-N film deposited at a N2 flow ratio of 20% has a low resistivity of 250 mW-cm. The Cu/Ta-Si-N (10 nm)/Si system is thermally stable at higher than 650°C. The leakage current density of junction diode is lower than 10-6A/cm2 after annealing at 600°C for one hour. Due to its very low dielectric constant, high thermal stability, process compatibility, and controllable porosity, surfactant-templated mesoporous silica film is consider to be one of the most promising low-k dielectric materials. The porous silica film developed by NTU Chemical Engineering Process Laboratory was used as low-k dielectric layer. Low-power O2 plasma treatment or low-temperature vacuum curing was utilized to replace conventional high-temperature calcination to remove the template. O2 plasma removed the template successfully, however, dielectric constant of resulted silica film was higher. H2 plasma was used to modify the film to be hydrophobic. H2 plasma was not as effective as HMDS in surface modification. To integrate copper and low-k dielectric, thermal stressing effects on resistance and stress of barrier/SiO2/Si and Cu/barrier/SiO2/Si systems were also evaluated by XRD, AFM, and TEM. Mechanism of stress migration is proposed and discussed.