標題: 寬頻用戶端閘道器:設計,實作與效能量測
Broadband Residential Gateway:Design, Implementation and Benchmarking
作者: 陳文瑞
Chen, Wen-Ruei
林 盈 達
Ying-Dar, Lin
資訊學院資訊學程
關鍵字: 用戶端閘道器;內嵌式系統;系統單晶片;residential gateway;home gateway;telecommunication service;system-on-a-chip;embedded platform;embedded system design
公開日期: 2001
摘要: 用戶端閘道器是一個在硬體的運算平台上的軟體應用,它可以提供網路連接與增進家電設備的自動化與智能化,以達成智慧型住宅之願景。 在本論文中,我們將探討實作一個符合規格的用戶端閘道器之過程。它包括(1)考量與訂定產品規格、(2)系統架構之設計與原型實作、(3)系統效能之評估與調較。硬體的平台是一顆高度整合的晶片(SOC),此顆晶片主要包括一個MIPS處理器的核心,一個Ethernet MAC控制器,一個ADSL DSP Engine,一個串列阜,及一些周邊設備。主要實作的軟體功能包括橋接器,NAT,DHCP,SNMP,TFTP,Web Server以及命令列介面與檔案系統等。此外,我們也將探討不同的軟體設計,對系統效能所造成的影響包括(1) 軟體的架構、(2) 輸出入資料暫存的架構、(3) 橋接器的設計: 直接轉送或暫存後再轉送。 最後,我們將展示實作寬頻用戶端閘道器的原型及其功能,並展示所測量之數據與結果。由測試結果,我們發現(1)與好的架構比較,較差架構之總處理量僅有其3.5%。(2) 動態分配暫存空間較固定分配有效率。(3) 直接處理封包較暫存後再處理在低封包率時有效率,但是若傳輸速度提升到某個極限,例如4000封包/秒,暫存後再處理較直接處理封包有效率。這些結果有助於未來類似產品之設計。
A residential gateway is a software application hosted on a computing platform. It offers device-networking functionality and increases the intelligence of a home. This thesis discusses the process by which a residential gateway is developed. The process includes (1) survey and definition of the system’s specification, (2) architecture design and implementation (3) performance evaluation and regulation. The hardware platform of the residential gateway uses a highly integrated system-on-a-chip which integrates a MIPS processor core, an Ethernet MAC, an ADSL DSP engine and various peripheral devices. The major software features implemented on the residential gateway include bridging, NAT, DHCP, SNMP, TFTP, a web server, command line shell and file system. The performance of the new design is explored addressing (1) software architecture, (2) I/O and buffering architecture, (3) cut-through and store-and-forward bridging. Finally, a prototype of the residential gateway is presented and pertinent experimental results are shown. Test result reveal that (1) unlike with good architecture, the throughput of the system is only 3.5% with poor architecture; (2) the dynamic buffer location architecture is more efficient than the fixed buffer location architecture, and (3) directly processing the received packets is more efficient then the store-and–forward mechanism. However, the throughput of the store-and-forward mechanism is better than that of directly processing at a transmission rate above 4000 packets per second. These experimental results are helpful in designing other, similar products.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT901706001
http://hdl.handle.net/11536/69632
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