使用於射頻收發器的一個低寄生雜頻之互補式金氧半2.4GHz 頻率合成器

Abstract

本論文實現了一個新型的電荷泵電路。這個電路具有完美的電流匹配特性，且可應用於2.4GHz的頻率合成電路上，用以有效地壓制雜頻的產生。實驗結果顯示本電路可使雜頻信號較主信號小七十分貝。根據其他研究指出：使用與本論文相似工作原理的電荷泵，可使雜頻信號比主信號低七十至七十五分貝。通常若使用傳統的電荷泵，雜頻信號約只比主信號小五十至六十分貝。因此本論文所提出的電路明顯地可有效壓低寄生信號的強度。 本論文中所提出的鎖相迴路式頻率合成器是以台灣積體電路零點二五微米數位類比混合式金氧半製程實現，此製程具有一層複晶矽和五層金屬。所有的電感和變容器都整合於晶片上。當使用兩伏特電源電壓時，整個晶片消耗37.4mW，晶片面積為2.56mm2。 簡而言之，本論文實現了一個低雜頻、高整合度的鎖相迴路式頻率合成器。其可應用於實現一個低成本、低消耗功率、可攜度高的無線傳收器。

This thesis implements a novel charge pump circuit with perfect current matching characteristics to be used in 2.4GHz frequency synthesizer. Conventional frequency synthesizers exhibit –50dBc ~ -60dBc spurious tones @ fref. The novel charge pump circuit that is proposed in this thesis can suppress spurious tones effectively, and can be realized easily. In this work, the measurement results exhibit the spurious tones of –70dBc @ fref below carry. There are other works with the same purpose and use different type of charge pump circuit from our approach which can achieved spurious tones of –70 ~ -75 dBc @ fref below carry as well. However, these approaches suffer clock feedthrough, and charge sharing. This PLL-based frequency synthesizers is implemented with 0.25um 1P5M mixed-mode CMOS process. All the inductors and varactors are on chip. It Consumes 37.4mW from a 2.2-V supply and occupies 2.56mm2. In summary, this work presents a low-spurious-tones and high integration PLL-based frequency synthesizer for a low cost, low power, and high portability transceiver solutions.