標題: 整合缺陷點數與群聚指標之積體電路良率模式
An Integrated Circuit (IC) Yield Model Considering
作者: 許志瑋
CHIC-WEI HSU
唐麗英
Lee-Ing Tong
工業工程與管理學系
關鍵字: 積體電路;缺陷點;群聚現象;群聚指標;良率模式;倒傳遞網路;Integrated circuitindex;defect;cluster;cluster;yield model;Backpropagation network
公開日期: 2002
摘要: 晶圓的良率(yield)是衡量積體電路製造業者生產能力的一個重要指標,影響良率高低的因素有很多,其中晶圓上缺陷點(defect)數的多寡及缺陷點的群聚(clustering)程度是決定晶圓良率高低的重要因素。近年來隨著晶圓面積不斷增大,晶圓上缺陷點的群聚現象越來越明顯,許多中外文獻雖然針對這個群聚現象提出了各種不同的群聚指標來衡量缺陷點群聚的嚴重程度,然而這些群聚衡量指標各有不完善之處,尤其是當缺陷的分佈呈現環狀分佈時現有之衡量群聚程度之指標皆無法偵測出。因此本研究首先發展了一個可有效偵測環狀群聚現象的指標,再進而整合此環狀群聚指標、及現有之群聚指標與缺陷點數,利用倒傳遞類神經網路(Backpropagation network, BPN)來架構一個良率模式,最後並以模擬與實際晶圓資料來驗證本研究所提之良率模式比業界常用的負二項良率模式以及現有文獻之修正後的良率模式為佳。
Yield is always the key point to evaluate the ability of manufacturing for the Integrated circuit (IC) manufacturer. There are two major factors affecting the IC yield. One is the total number of defects on a wafer and the other is the degree of defects clustering on a wafer. As the wafer size increase, the defects clustering phenomenon tends to get serious. Though there are many kinds of cluster index proposed to evaluate the degree of defects clustering, it is still very difficult to quantify the defects clustering phenomenon perfectly by using these cluster indices we had, especially when it comes to an edge type defects pattern on the wafer. In this paper, an “constellation index” which can detect the edge type defects pattern effectively has been developed first. Then an IC yield model which using Backpropagation network (BPN) considering the “constellation index”, the cluster index CIR and defects numbers has been proposed. To verify the effectiveness of the proposed IC yield model, a simulation experiment and a case study are presented. Comparisons are also made among the Negative Binomial yield model, modified yield model and the proposed yield model.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT910031011
http://hdl.handle.net/11536/69768
顯示於類別:畢業論文