多層導體連線銅電鍍與電拋光製程之研究

Abstract

在多層導體連線銅鑲嵌製程中，電鍍技術已經成為沉積銅導線的主要方法。這是由於電鍍技術擁有低成本、高產能、優異的填洞能力等優勢。為了得到次0.2微米無缺陷的銅溝槽與引洞，不同的電鍍溶液成分與製程參數不斷的在文獻上被發表與研究。在生產線上，精確的控制銅電鍍過程是相當重要但同時也是相當困難的。無缺陷的銅電鍍通常只在很嚴苛的製程參數下才能得到。此外，在電鍍過程中，電鍍液的電化學特性非常複雜以致於很難預測與控制，主要由於電鍍液通常為成分未知之商業鍍液，且鍍液中的添加劑會隨著電鍍的過程裂解、變質與互相反應。因此，銅電鍍仍需要更多的研究來釐清其電化學行為。此論文前半部份將探討極化現象、有機添加劑、熱退火及脈波參數對銅電鍍的影響，並期達到銅膜性質與填洞能力之最佳化。 在下一世代的半導體製程技術中，極低介電常數材料(介電常數小於3)將整合至銅鑲嵌製程以增加元件速度。然而，引進新材料將伴隨新的製程變數，尤其低介電常數材料其機械性質較二氧化矽為差，傳統的化學機械研磨製程容易將其損壞。近來，銅電拋光技術正被積極研究用來取代銅化學機械研磨製程。它是利用外加電壓取代機械力來移除多餘的銅層，其無應力之特質可維持低介電常數材料之特性，此外，銅電拋光技術又擁有高拋光速率、低溶液消耗、無研磨砥粒及無刮痕等優點，利用它可得到一平滑且乾淨的銅層。本論文後半段將研究銅電拋光技術的電化學行為及平坦化機制。其中，有機酸添加劑將被用來達成晶圓製程上的超拋光效果。

Electroplating (ECP) has been the leading method for Damascene Cu deposition in multilevel interconnection due to its low cost, high throughput and superior gap-filling capability. To achieve defect-free filling in sub-0.2 □m trenches/vias, various plating baths and process conditions are investigated in the literatures. Precisely control of Cu ECP is both essential and difficult. Defect-free filling is usually obtained at a rigidly process window. Furthermore the plating chemistries are too complicated to predict and control because they are usually proprietary and they may cleave, decay and co-react during Cu ECP. Further studies are needed to realize the electrochemical behaviors of Cu ECP. In this thesis, polarization, organic additives, post-ECP annealing and pulse current of Cu ECP are studied to optimize the film properties and gap-filling capabilities. For next technology node, super-low-k dielectrics (k<3) will be adopted in the Cu Damascene process to reduce RC delay of interconnect. However, integrating new materials would face with many process challenges. In particular, low-k dielectrics with porous structure would be mechanically weaker than silicon dioxide. Typically chemical mechanical polishing (CMP) processes will cause sever damage on low-k films. Cu electropolishing (EP) is recently explored as a replacement of Cu-CMP. An applied electric field is substituted for the mechanical force component in CMP to remove excess Cu layers. The stress-free characteristic of Cu EP can handle low-k dielectrics. Furthermore, Cu EP has the advantages of high polishing rate, low waste stream, no abrasive and no scratching. It can produce a clean and scratch-free Cu surface. In this thesis, the electrochemical behaviors and micro-leveling mechanism of Cu EP are studied. Organic acid additives are also used to achieve “super-polishing” in wafer processing.